JPH01106232A - Microprocessor analyzer - Google Patents

Abstract

PURPOSE:To attain the detection of an unrestricted address range by the addition of the small number of hardwares by inputting the upper address of an address bus to an address conversion circuit and inputting its lower address and a data output >=1 bit from the address conversion circuit to a trace word detecting circuit. CONSTITUTION:An address conversion RAM 2 and a trace word detection RAM 3 are set up as shown in graphics. When a target address is included within the range from 0C000H to 0FFFFH, the D0 output of the RAM 2 is turned to '1', an AND gate 7 is opened, and since its D1 output is '0', an address input A15 to the RAM 3 is turned to '0' and its output D3 is turned to '1', a trace word signal (TRW) is outputted. Even when the target address is in the range from 10000H to 13FFFH, the trace word signal (TRW) is also outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improving the tracing capabilities of microprocessor analyzers.

[Prior Art] Conventionally, there has been a microprocessor analyzer used to analyze the operation of microprocessor (hereinafter abbreviated as μP) applied equipment. This μP analyzer has a trace memory to record the instructions and their addresses executed by the μP to be tested (referred to as the target μP) in order to analyze the operation of the μP to be tested and its peripheral logic circuits. We are prepared.

The general operation of a μP analyzer having such a configuration is as follows. When inspecting a target system that behaves abnormally, a condition that is estimated to cause an abnormality is set as a trigger word and a trace operation is started. The trace operation refers to an operation in which information such as the address bus and data bus of the target μP is sequentially recorded in the trace memory. The trace memory is configured so that when the record becomes full, cyclic writing is performed to overwrite it again starting from the first address.

If a trigger word is detected during this trace operation, the trace operation is stopped. Thereafter, the cause of the abnormal phenomenon can be ascertained by reading trace data from the trace memory and analyzing it before the trigger word detection time.

[Problems to be Solved by the Invention] However, since the capacity of the trace memory is not infinite, there may be cases where the part that caused the abnormality cannot be stored in the trace memory. In order to eliminate such problems, only the conditions (trace words) that are likely to cause an error are stored in the trace memory, and no other data is stored in the trace memory. There is a tracing method that can be used effectively. This method is called multi-trace.

A trace word detection circuit that detects trace words is required to be able to set multiple trace words or a range of specific addresses.1 Usually, a random access memory (RAM) 41 is used as shown in FIG. Consists of. Target μP is used for address input of RAM41.
address from the address bus, and the data output of the RAM is the trace word output. RAM in advance
Data “1” to multiple addresses or a specific address range
By setting this and clearing other addresses with the data block, it is possible to set multiple trace words or a range of specific addresses.

An 8-bit μP with a 16-bit address bus can be realized by using a RAM with a 64Kxl bit configuration as shown in Figure 4, but a 16-bit μP with a 20-bit or 24-bit address bus is also possible. In some cases, 1
A RAM of 1 megabyte x 1 bit or 16 megabytes x 1 bit is required. If this were to be achieved using RAM chips currently on the market, a large number of RAM chips would be required and would be expensive.

To solve this problem, there is a method as shown in FIG. 5, for example. The address bus of the target μP is divided into upper and lower parts, each of which is input to the addresses of two RAMs 51 and 52, and the data outputs of the two RAMs are passed through an AND gate 53 to output a trace word signal TRW.

This method has the disadvantage that when setting a specific address range, it cannot be set unless the upper address is in a fixed area.

Therefore, in the example of FIG. 5, the target μP address 0C
OOOH (H is a hexadecimal symbol) to 13FFFH
Setting the range becomes impossible.

As a means to solve this problem, for example, as shown in FIG. 6, the circuit in FIG.
) can be considered. In the example of FIG. 6, RAM61.
The RAM 62 can detect the range from OCO00H to 0FFFFH, and the RAM 63 and RAM 64 can detect the range from 100OOH to 13FFFFH. If address range detection without restrictions is realized in this way, there is a problem in that it requires twice as many detection circuits and becomes expensive.The purpose of the present invention is to solve such problems, and to realize address range detection. The object of the present invention is to provide a microprocessor analyzer that can be implemented without any limitations at a low cost.

[Means for Solving the Problems] In order to achieve such an object, the present invention samples designated bus data of a target microprocessor, sequentially stores it in a trace memory, and stores it in a trigger memory.
When a word is detected, the microprocessor stops storing it in memory after sampling the set number of samples, and analyzes the microprocessor's operation by referring to the trace data before and after detecting the trigger word.
In the analyzer, the upper address of the address bus of the target microprocessor is connected to the address input of an address translation circuit, and the lower address and one or more bits of data output of said address translation circuit are connected to the address input of a trace word detection circuit. trace word detection means for gating the data output of the trace word detection circuit with another data output of the address conversion circuit to output a trace word signal for controlling the recording operation in the trace memory; .

The target microprocessor's address bus, data bus, and status signals can be
and a trigger detection circuit that outputs a trigger signal when a word condition is met.

The present invention is characterized by comprising a memory address control circuit that controls the address of the trace memory using the trace word signal and stops counting after a preset counting operation using the trigger signal.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a μP analyzer according to the present invention. In FIG. 1, 1 is the target μP,
2 is an address conversion circuit (RAM), 3 is a trace word detection circuit (RAM), 4 is a trigger detection circuit, 5 is a memory address control circuit that generates the address to be stored in the trace memory, and 6 is the address of the target μP. 7 is a computer (hereinafter abbreviated as control CPU) for controlling the μP analyzer, and 8 is an AND gate.

9 is an address bus of the target μP, 10 is a data bus through which data and status signals of the target μP are transmitted, and 11 is a control CPU bus.

The upper bus of the address bus signal 9 of the target μP is connected to the input of the address conversion RAM 2, one output is connected to the input of the AND gate 8, and the other output is connected to the input of the trace word detection RAM 2. . trace·
The lower bus of the 1-dress bus 9 of the target μP is connected to the other input terminal of the word detection RAM 2, and the output is an AND
Connected to the input of gate 8.

A portion A indicated by a broken line in FIG. 1 is a trace word signal T which is a match signal when the contents of the address bus 9 of the target μP match a condition set in advance from the control CPU 7 through the control CPU bus 11.
It outputs RW and is referred to here as a trace word detection means.

Trigger detection circuit 4 has inputs connected to target address bus 9 and data bus 10.

A trigger signal T, which is a match signal, is generated when the contents of the bus of the target μP match a condition set in advance from the control CPU 7 to the control CPU bus 11.
Output RG.

The memory address control circuit 5 has an AND gate 8 at its input.
The trace word output TRW of the trigger detection circuit 4 is connected to the trigger word output TRG of the trigger detection circuit 4, and the output is the trace word output TRW of the trigger detection circuit 4.
Connected to memory 6. A target address bus 9 and a data bus are connected to the inputs of the trace memory 6. Furthermore, memory address control circuit 5 and trace memory 6 are also connected to control CPU bus 11 .

FIG. 2 shows a specific example of the trace word detection means (broken line portion) A in FIG. 111, in which the address translation circuit (RAM) is configured in 2 bits for the sake of simplicity.

The upper bus (TA15 to TA23) of target address bus 9 is connected to the address input of address translation RAM2, and the lower bus (TAO to TA14) is connected to the address input of trace word detection RAM3.

The operation in such a configuration will be explained next.

First, the operation of trace word detection will be explained.

Figure 3 shows the configuration shown in Figure 2, with addresses 0COOOH to 13.
This is the content set by the control CPU 7 when detecting the range up to FFFFH.

In the address conversion RAM 2, for Do, only addresses 1 and 2fIr are '1', and all other addresses are '1'.
0", and for Dl, address 1 is 2'
O'' and set the 2nd address to ``1''.

Trace word detection RAM3 starts from address 4000 to 0
Set addresses up to 7FFFH to “1” and other addresses to “0”.
”.

By setting in this way, the target address will be in the range 0COOOH to 0FFFFH (TA15 to T
A23 → 1, TAO-TA14 → 4000H ~ 7FFF
In H), the DO output of the address conversion RAM2 becomes "1", the AND gate 7 opens, and the D1 output is 'O', so the address input A1 of the trace word detection RAM3
5 becomes 0" and the output D3 becomes "1", so the trace word signal TRW is output. Also, the target signal
Address range from 100OOH to 13 F F F H (TA15~TA23→2
, TAO-TA14→OH~3FFFH), the Do output of the address conversion RAM 2 becomes "1", the AND gate 7 opens, and the Dl output is 11111, so the address input A15 of the trace word detection RAM 3 becomes "121".
As a result, the output D3 becomes 1'', and the trace word signal TRW is output.

Here, to simplify the explanation, we will explain the address conversion RAM D.
Although the explanation has been made assuming that one output is one bit, the same operation is possible with two or more bits.

Further, in the present invention, the detection width of the address range is limited by the capacity of the trace word detection RAM, but even in the example of FIG. 5, the range of bytes can be set to 64, which does not pose a problem in normal use.

Trace word signal TRW detected in this way
is input to the memory address control circuit 5. memory·
The address control circuit 5 controls the address of the trace memory using the trace word signal, and performs sampling after counting a preset number of counts (sampling number) after the arrival of the trigger signal detected by the trigger detection circuit 4. Stop.

[Effects of the Invention] According to the present invention, unlimited address range detection can be realized with the addition of a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of trace word detection means, and FIG. 3 is an explanation for explaining the operation of the trace word detection means. 4 to 6 are diagrams for explaining conventional trace word detection. DESCRIPTION OF SYMBOLS 1...Target μP, A...Trace word detection means, 2...Address conversion circuit, 3...Trace word detection circuit, 4...Trigger detection circuit, 5...
・Memory address control circuit, 6...Trace memory, 7...Control CPU, 8...Gate, 9
...Address bus, 10...Data bus, 11
...Control CPU bus. 3rd cause 64 me/lO:'', ll-memo, su

Claims (1)

[Claims] Specified bus data of the target microprocessor is sampled and sequentially stored in a trace memory, and when a trigger word is detected, a set number of samples are sampled and then stored in the memory. In a microprocessor analyzer that can analyze the operation of a microprocessor by referring to trace data before and after detecting a trigger word, the upper address of the address bus of the target microprocessor is The data output of the lower address and one or more bits of the address conversion circuit is connected to the address input of the trace word detection circuit, and the data output of the trace word detection circuit is connected to other data of the address conversion circuit. trace word detection means for outputting a trace word signal that controls the recording operation to the trace memory by gating at the output; and address bus, data bus, and status signals of the target microprocessor are preset. triggered
a trigger detection circuit that outputs a trigger signal when a word condition is met; and a memory that controls the address of the trace memory by the trace word signal and stops counting after a preset counting operation by the trigger signal. - A microprocessor analyzer characterized by being equipped with an address control circuit.