JPH01106647A - Check method for transmission signal converter - Google Patents

Abstract

PURPOSE:To obtain very high transmission quality by applying phase synchronization when bit comparison between a signal before conversion and a signal decoded by inverse conversion shows dissidence so as to apply bit comparison again thereby preventing erroneous changeover. CONSTITUTION:A digital transmission signal inputted to a transmission signal converter 1 is converted into a prescribed form. The converted signal is inverted into the original form. Then the inverted signal and the signal before the conversion are subjected to phase synchronization. Both the signals subjected to phase synchronization in this way are subjected to bit comparison in the unit of a prescribed period and the coincidence of both the signals is discriminated from the result of bit comparison. If the dissidence of the both is confirmed, the phase synchronization and the comparison are repeated in the succeeding units. If the discrimination of dissidence for a prescribed number of units is obtained consecutively, a fault of the converter 1 is informed to a standby equipment and a changeover device to other line.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [6I Required] The present invention This relates to a method of checking a transmission signal converter by inversely converting the transmission signal converted and output by the signal converter and comparing it bit by bit with the digital transmission signal before conversion, and it is possible to always obtain error-free check results. For this purpose, the transmission signal converted to a predetermined format by a transmission signal converter is inversely converted to the original format, and the phase of the moderated digital transmission signal and the digital transmission signal before conversion is adjusted. The bits of both synchronized and phase-synchronized transmission signals are compared in a fixed period of time, and based on the comparison result, it is determined whether the two transmission signals match or do not match. When a mismatch is determined, both signals are The phase synchronization and matching are repeated for subsequent units, and when a predetermined number of units are consecutively judged as inconsistent, an abnormality in the transmission signal conversion device is notified.

[Industrial Field of Application] The present invention relates to a method for checking a transmission signal conversion device by inversely converting a transmission signal converted and output by a transmission signal conversion device and comparing it bit by bit with a digital transmission signal before conversion. .

At the terminal station of digital transmission, multiple transmission signals obtained from the lower side are converted (multiplexed) into one digital transmission signal and sent to the upper side, and the digital transmission signal given from the upper side is It is converted (separated) into multiple digital transmission signals and sent to the lower side.

If an abnormality occurs in the equipment that performs these signal conversions, the digital signal transmission system from the lower side to the upper side will go down, making the transmission system unusable. Checks are carried out all the time, and when an abnormality in the equipment is confirmed by this check, a switch is made from the current one to the standby one or a switched line.

[Prior Art] FIG. 8 shows a flowchart of the above-mentioned check procedure conventionally performed, and FIG. 9 explains its operation.

In FIG. 8, when one of the current signal transmission devices is specified, the count value C is set to 1 (step 800), and the inversely converted transmission signal converted by that device and the original digital The phase of the transmission signal is synchronized (step 802).

Then, each bit of both transmission signals is compared for a certain period of time Δt (one stage) (step 804),
- The presence or absence of an error is determined (step 806).

At this time, it is confirmed that there are no bit errors (YES in step 806), and if both transmission signals match, it is determined that this device is operating normally (
Step 808), Specify the next device (Step 810)
The abnormality check operation is then repeated for that device.

That is, once it is confirmed that a transmission signal with the same content as before conversion is obtained at the output side of the device, the normal operation of that device is confirmed, and a check is performed on the next device.

Therefore, all devices can be checked in a short time.
Therefore, it is possible to greatly shorten the check scan period and speed up the check.

Also, during the check scan, if it is confirmed by bit matching that there is a difference in content between the transmission signal before and after conversion in any device (N in step 806).
O), the count value C is incremented (step 812), and in the next fixed period Δt (step 804), the matching of each pin 1 to 1 (step 804) and the determination of the presence or absence of a bit error (step 806) are performed again. .

If it is confirmed that there are no bit errors at this time (YES at step 806), it is considered that the previous determination that there was a bit error was due to a one-off bit error or a burst error, and therefore the device is operating normally. A determination is made to that effect (step 808).

However, if a bit error is confirmed at that time (NO in step 806), each bit is compared in the next period Δt (step 804) and the presence or absence of a bit error is determined (step 806) in the same way. is repeated until the count value C reaches a predetermined value (value 3 in FIG. 8) as long as a bit error is confirmed (NO in step 806).

Then, bit matching is performed that number of times (step 804).
) and the determination of the presence or absence of bit errors (step 806) are repeated (YES in step 814), it is confirmed that the device currently being checked is operating abnormally (step 816), and a spare device or another A switch to the line is made (step 818).

In this way, it is possible to avoid the line being cut off and the entire transmission system going down even though there is an abnormality in the equipment.

In reality, bit error determination (step 806) is performed when a predetermined number of bit errors or more are confirmed, and device abnormality is confirmed when the determination is repeated a predetermined number of times (stages). Therefore, the period Δt is predetermined based on the bit error rate, which is the threshold value for the device check, and the number of error pits, which is the criterion for determining bit errors.

As described above, in the conventional technology, as can be understood from FIG. ), as can be understood from FIG.
) sometimes there is no phase synchronization of the two transmitted signals.

Therefore, when a phase shift occurs due to a momentary interruption of the transmission signal as shown in (C) of the same figure, the phase shift continues even after that, and therefore, even though the device currently being checked is operating normally, the It is determined at the next stage that an abnormality has occurred, and as a result, switching to a standby device or another line is performed.

[Problems to be Solved by the Invention] For this reason, in the past, there has been a problem in that switching causes momentary interruptions in the lines of the transmission system from the lower side to the upper side, degrading the transmission quality.

The present invention has been made in view of the above circumstances, and its purpose is to prevent erroneous transmission to backup equipment or another line even if a phase shift occurs between the transmission signals before and after conversion due to a momentary interruption of the transmission signal. To provide a check method that can reliably prevent switching and prevent instantaneous disconnection of a line due to the switching.

[Means for Solving the Problems] FIG. 1 provides a detailed explanation of the present invention, in which a transmission signal conversion device 1 converts an input digital transmission signal into a predetermined format.

The transmission signal converted by the transmission signal converter 1 is then inversely converted to its original format (2), and the inversely converted digital transmission signal and the digital transmission signal before conversion are phase-synchronized (
3).

Both transmission signals, which are phase-synchronized in this way, are compared every pitch from 1 to 1 for a certain period (Δt) (4)
Based on the comparison result, it is determined whether the two transmission signals match or do not match (5).

If a discrepancy between the two is confirmed at that time (5: YES)
, their phase synchronization (3) and matching (4) are repeated for subsequent units (YES at 6), and when a determination of mismatch is made for a predetermined number of units (YES at 5) consecutively. (YES in 6), the abnormality in the transmission signal converter 1 is notified to the standby device or to the device that performs switching to another line.

[Operation] In the present invention, when it is determined that the transmission signal does not match, (5
YES); Since phase synchronization between the pre-conversion transmission signal and the inversely-converted one (3) is performed, each bit of both transmission signals is matched (4), so instantaneous interruptions in the transmission signal, etc. Even if a phase shift occurs between the two transmission signals, when the respective bits of both transmission signals are matched (4), the pins 1 to 1 are synchronized.

Therefore, corresponding bits are always matched (4).

[Example] Hereinafter, a preferred example of the method according to the present invention will be described based on the drawings.

FIG. 2 shows a simplified terminal station 101M4 configuration inserted between the upper side and the lower side to transmit digital signals between the two. The three digital signals are sent to the current multiplexing circuit 14 (the first
(corresponding to the transmission signal conversion bag @1 in the figure).

This multiplexing circuit 14 performs transmission signal conversion to multiplex the transmission signal 200 to obtain the transmission signal 202, and the converted transmission signal 202 is sent to the upper side of the transmission line 1.
It is being transmitted to 2LJ.

Note that other working multiplexing circuits and their backup circuits are omitted in FIG. 2, and when an abnormality occurs in the multiplexing circuit 14, the circuit is switched to its backup circuit.

The transmission signal 202 obtained by the current multiplexing circuit 14 is given to the standby separation circuit 16, and the separation circuit 16 obtains a transmission signal 204 that is the same as the transmission signal 200, although the phase is different.

Note that the currently used separation circuit is omitted in FIG. 2, and the separation circuit is used for digital signal transmission from the upper side to the lower side.

The transmission signal obtained by this separation circuit 16 and the multiplexing circuit 14
The transmission signal 200 before the conversion is applied to the phase synchronization circuit 18, and the phase synchronization circuit 18 synchronizes the phases of the image transmission signals 200 and 204.

FIG. 3 (A>) shows the configuration of the phase synchronization circuit 18, and transmits data @200, 204.

The clock is provided on flip 70 tube 20.22.

The Q signals of the flip-flops 20 and 22 are applied to the fixed delay circuit 24 and the elastic memory 26, respectively, and the clock of the transmission signal 200 is applied to the read clock input of the elastic memory 26.

Roughly fixed delay circuit 24 output data and transmission signal 200
The clock is supplied to the variable delay circuit 28, and the variable delay circuit 28 is supplied with a select signal.

Also, the output data 300 of the elastic memory 26 is E
The output data 302 of the variable delay circuit 28 is also applied to the OR gate 30.

The output data 304 of the EOR gate 30 is applied to the AND date 34 via the flip-flop 32, and the clock of the transmission signal 200 is applied to the flip-flop 32 and the AND gate 34, respectively.

Further, FIG. 2B shows the structure of the variable delay circuit 28, which is composed of a selector 36 and a shift register 38, which output data 302 in response to a select signal.

Among them, the shift register 38 is a flip-flop 40-1.40-2.40-3.40-4---40-
The output data of the fixed delay circuit 24 and each Q output are input to the selector 36.

Furthermore, the clock of the transmission signal 200 is set to each flip-flop 40-1.40-2.40-3.40-4...40
- (n-1), 40-n, and therefore each of their Q outputs is delayed with respect to the output data of the fixed delay circuit 24 by the number of stages.

The other selector 36 selects one of them as data 302 according to the select signal, and the FO
In the R gate 30, the data 302 and the output data 300 of the elastic memory 26 are subjected to EOR to perform matching (verification) of the transmission signals 200.degree. 204 on a bit-by-bit basis.

The output data is given to the counting circuit 42 in FIG. 2 in synchronization with the clock of the transmission signal 200, and the counting circuit 42 counts data 304.

The data 304 is the data 3 of the transmission signals 200, 204.
Since 02,300 is EORt, .

This count value is given to a control circuit 44, and counting control of the counting circuit 42 is performed by this control circuit 44.

A select signal is also supplied from the control circuit 44 to the variable delay circuit 28 of the phase synchronization circuit 18, whereby the transfer signals 200, 204 (data 302, 300>) are phase synchronized.

The transmission signal 204 after inverse conversion given to the phase synchronization circuit 18 is delayed by a certain fixed delay by various gates, flips 70, etc., and the multiplexing circuit 142 separation circuit 16. It is delayed with respect to the transmission signal 200 before conversion by an amount determined from the dynamically varying delay caused by the elastic memory 26 and the like.

Therefore, in the variable delay circuit 28, the data 302 is
is delayed, which causes the data 302.300
(i.e., the quantity transmission signals 200, 204) are phase-locked.

In order to perform phase synchronization of these data 302, 300, the control circuit 44 performs processing according to the flow chart shown in FIG.

In FIG. 4, first, the value n indicating the number of selected stages of the shift register 38 by the selector 36 is reset, and a select signal containing this value is output to the selector 36 (step 400).

Then, the counting circuit 42 is instructed to start bit error counting (step 402), and after that, when it is confirmed that a predetermined time has elapsed (YES in step 404),
The counting circuit 42 is instructed to end bit error counting, and the counted value is read (step 406).

If the number of bit errors roughly indicated by the count value is not less than the predetermined number (No in step 408), 11an indicating the number of selection stages (i.e. delay mother) is incremented (step 410), and the count of bit errors is It starts again (step 402).

Therefore, by repeating the above operations, the phase of the data 302 is successively delayed by the variable delay circuit 28 in a direction in which the phase is synchronized with that of the data 300.

After that, the bit error count value becomes O (step 40
When it is confirmed that the phases of both data 302°300 (that is, both transmission signals 200, 204>) are matched (YES in step 8), a procedure for completing this process is performed (step 41).
2>, the multiplexing circuit 14 becomes available for checking.

In FIG. 5, the phase synchronization effect when the phase difference between the two transmission signals 200 and 204 is 2 bits is explained using a timing chart.
The phase shift between 00.204 and 2 bits is
In the figure (B), when the value n is incremented, the phase shift is reduced to 1 bit, and in the figure (C), when the value n is incremented again, the phase shift becomes 0 bit, and the phase of the two is synchronized.

FIG. 6 is a flowchart showing the procedure for checking the multiplexing circuit 14 and switching it to the standby side in the event of an abnormality.

Note that steps having the same content as those in FIG. 8 described above are given the same reference numerals, and phase synchronization (step 802) is performed as described above.

Here, in this embodiment, confirmation of the error (step 8) is performed.
Every time No> is performed in 06, the transmission signal 200.20
4 phase synchronization (step 802) is performed before bit verification by matching each bit (step 804).

Therefore, if a phase shift occurs between the image transmission signals 200 and 204 due to a momentary signal interruption as shown in FIG. 7 (A>), the phase synchronization between the transmission signals 200 and 204 will be lost again. The phase shift is eliminated, and the normal operation of the multiplexing circuit 14 is confirmed next time.

In addition, in the same figure (B), even the second time, the phase shift is 20
This occurs between 0 and 204, but this does not occur the third time, and therefore the normal operation of the multiplexing circuit 14 is confirmed at that time.

As described above, according to this embodiment, if a bit error is confirmed by matching each bit of the signal 204 obtained by inversely converting the transmission signal 202 after conversion with the transmission signal 200 before conversion, the phase synchronization between the two is detected. Since the bits are matched after checking the multiplexing circuit 14 again, even if a momentary signal interruption occurs during the check of the multiplexing circuit 14 and a phase shift occurs between the transmission signals 200 and 204, the phase shift is resolved. The matching of each bit is performed again from
It is possible to completely prevent instantaneous interruption of the signal transmission path due to erroneous switching of signal transmission line 4 to the standby side, and as a result, extremely high quality transmission can be performed.

Furthermore, according to this embodiment, even if the multiplexing circuit 14 is operating normally, it will not be accidentally switched to the backup side due to a momentary line interruption, so maintenance personnel can switch it to the active side. Therefore, it is possible to facilitate maintenance and improve the reliability of the terminal station 10.

[Effects of the Invention] As explained above, according to the present invention, when a mismatch between the transmission signal before conversion and the transmission signal restored by inverse conversion is confirmed by bit matching, the phase synchronization between the two is confirmed. Since the bits of the image transmission signal are matched after the image transmission signal is taken, even if a phase shift occurs between the two due to a momentary interruption of the line, the bits are matched again after this has been resolved, thus eliminating errors caused by this phase shift. Therefore, it is possible to completely prevent instantaneous line interruptions due to such switching, and as a result, even if the line interruption occurs for a short period of time, instantaneous interruptions in the transmission line can be reliably prevented and extremely high quality can be achieved. This makes it possible to obtain high transmission quality.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the principle of the invention, Figure 2 is a diagram explaining the configuration of a digital transmission terminal, Figure 3 is a block diagram showing the configuration of the phase synchronization circuit shown in Figure 2, and Figure 4 is a diagram showing the phase synchronization circuit. Flowchart showing the procedure for synchronization processing, FIG. 5 is a timing chart explaining the phase synchronization effect in the embodiment, FIG. 6 is a flowchart explaining the check action in the embodiment, and FIG. 7 is an explanation of the check action in the embodiment. 8 are flowcharts showing the conventional method, and FIG. 9 is an explanatory diagram of the operation of the conventional method. 1... Transmission signal conversion device 2... Inverse conversion 3... Phase synchronization 4... Matching 5... Judgment of mismatch 6... Judgment of device abnormality 7... Abnormality notification 10... Terminal stations 12D, 12U... Transmission line 14... Multiplexing circuit 16 in current use... Separation circuit 18 on standby side... Phase synchronization circuit 42... Counting circuit 44... Control circuit

Claims (1)

[Claims] Inversely converting a transmission signal converted into a predetermined format by a transmission signal conversion device to the original format, synchronizing the phase of the inversely converted digital transmission signal and the digital transmission signal before conversion, The bits of both synchronized transmission signals are compared in units of a certain period, and based on the comparison result, it is determined whether the two transmission signals match or do not match. When a mismatch is determined, the phase synchronization of both transmission signals is determined. A transmission signal conversion device characterized in that the matching is repeated for subsequent units, and when a predetermined number of units are consecutively judged as inconsistent, an abnormality in the transmission signal conversion device is notified. Method for checking.