JPH01107155U - - Google Patents

Info

Publication number
JPH01107155U
JPH01107155U JP1988000921U JP92188U JPH01107155U JP H01107155 U JPH01107155 U JP H01107155U JP 1988000921 U JP1988000921 U JP 1988000921U JP 92188 U JP92188 U JP 92188U JP H01107155 U JPH01107155 U JP H01107155U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
island
insulator
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988000921U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988000921U priority Critical patent/JPH01107155U/ja
Publication of JPH01107155U publication Critical patent/JPH01107155U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の上面図、第2図は
第1図のA―A′断面図、第3図a,bは他の実
施例を示す平面図、断面図である。 1……集積回路チツプ、2……パツド、3……
導電体、4……絶縁体、5……アイランド、6…
…リード、7,7a,7b……ボンデイング線。
FIG. 1 is a top view of one embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, and FIGS. 3a and 3b are a plan view and a sectional view showing another embodiment. 1... integrated circuit chip, 2... pad, 3...
Conductor, 4... Insulator, 5... Island, 6...
...Lead, 7, 7a, 7b...bonding wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路チツプと該集積回路チツプを搭載する
部分(以下アイランドと称す)との間に導電体及
び絶縁体を配置することを特徴とする集積回路。
An integrated circuit characterized in that a conductor and an insulator are arranged between an integrated circuit chip and a part (hereinafter referred to as an island) on which the integrated circuit chip is mounted.
JP1988000921U 1988-01-07 1988-01-07 Pending JPH01107155U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988000921U JPH01107155U (en) 1988-01-07 1988-01-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988000921U JPH01107155U (en) 1988-01-07 1988-01-07

Publications (1)

Publication Number Publication Date
JPH01107155U true JPH01107155U (en) 1989-07-19

Family

ID=31200356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988000921U Pending JPH01107155U (en) 1988-01-07 1988-01-07

Country Status (1)

Country Link
JP (1) JPH01107155U (en)

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