JPH01107555A - Mis semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve an excess sidewall current and back gate bias effect by providing the same conductivity type high concentration diffused layer as that of a substrate on a substrate region of part of the top of the side face of the substrate in contact with a groove and in contact with the surface of the substrate without channel width by controlling the width of a sidewall insulating film. CONSTITUTION:A protrusion type insulating film 4 is formed on one semiconductor substrate 1, and with the film as a mask the same conductivity type impurity as that of the substrate 1 is implanted. Then, sidewall insulating films 7 are formed at both sidewalls of the protrusion of the insulating film, and with the films 4 and 7 as masks a groove 8 is formed by etching. Accordingly, the same conductivity type high concentration diffused layer as that of the substrate is provided only on a substrate region in contact with the part of the top of the side face of the substrate in contact with the groove and in contact with the substrate surface without channel width by controlling the width of the insulating film 7 with the groove type insulating isolating layer of necessary depth for the one substrate. Thus, its back gate bias effect can be suppressed, and the width of the sidewall insulating film is controlled, thereby forming the same conductivity type high concentration layer as that of the substrate only on the sidewall even if the channel width is small, and suppressing an excess sidewall current.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a MIS type semiconductor device having a trench type insulating layer and a method for manufacturing the same.

Conventional technology Conventionally, in MIS type semiconductor devices having a groove-type insulating separation layer, "IEEI Transaction on Elec. E TRANSACTIONON ELEC
TRON DKVICK, VOL, I! :D-32°NO2, 1986J P, 441-445 N, S
Higyo.

In 1985, a sloped groove-type insulating isolation layer structure was proposed, in which a sloped groove was formed and an impurity of the same conductivity type as the substrate was implanted using the slope.
Symposium on Buernis Eye Technology (
SYNPOSIUM ON VLSITECHNOLO
GY)P, 58-59, G, Fuse, atal, J
There is a trench-type isolation layer structure with oblique impurity implantation of the same conductivity type as the substrate, which was proposed in . The semiconductor substrate 1 is shown in FIG.
A cross-sectional view of an MIS type semiconductor device having a sloped groove-type insulating layer 11 when used as a mold is shown. FIG. 4 shows a cross-sectional view of a substrate for an MIS type semiconductor device having a groove type insulation isolation structure and having an oblique impurity implantation region 16 when the semiconductor substrate 1 is of P type.

In FIGS. 3 and 4, 1 is a P-type silicon substrate, 2 is an insulating film, 11 is a silicon oxide film, 14 is an impurity of the same conductivity type as the substrate 1, and 15, 15a, and 1!5b are formed by 14. This shows an impurity region of the same conductivity type as the substrate.

Problems to be Solved by the Invention However, in the semiconductor device shown in FIG. 3, which has the above-mentioned inclined trench-type insulating separation layer, vertical isolation, which is a characteristic of trench-type isolation, is not formed, and the slope angle process is difficult. It is difficult to control the above. In addition, in the semiconductor device shown in FIG. 4, the sidewall current is improved for devices with a large channel width, but impurities of the same conductivity type cannot be implanted only into the sidewalls of devices with a small channel width. Sidewall current has not been improved. Furthermore, it is necessary to control the impurity implantation angle, and in addition, the channel stop region 162L at the bottom of the trench type isolation layer
There was a problem in that impurity implantation into the substrate side region 15b in contact with the trench and the trench were performed at the same time. Furthermore, both of the above-mentioned amphibic conductor devices have a problem in that the back gate bias effect is large because impurities of the same conductivity type as the substrate are implanted into the entire side surface of the substrate in contact with the groove.

Means for Solving the Problems The present invention has a groove-shaped insulating separation layer of a necessary depth, and a substrate region that is in contact with the substrate surface in a part of the upper part of the side surface of the substrate that is in contact with the groove, regardless of the channel width. , a highly concentrated diffusion layer of the same conductivity type as the substrate is formed. This is a method of manufacturing a semiconductor device that suppresses excessive sidewall current, improves the back gate bias effect, and performs implantation of impurities of the same conductivity type as the substrate in a separate process using a simple manufacturing technology.

That is, the present invention includes a first step of forming a convex insulating film on one semiconductor substrate, a second step of implanting an impurity of the same conductivity type as the substrate using the insulating film as a mask, One of the semiconductors manufactured by a third step of forming a sidewall insulating film on both side walls of the convex portion of the insulating film, and a fourth step of forming a groove by etching using the insulating film and the sidewall insulating film as a mask. By controlling the width of the sidewall insulating film, the substrate region has a groove-type insulating separation layer with a depth required for the substrate, and is a part of the upper part of the side surface of the substrate in contact with the groove and in contact with the surface of the substrate, regardless of the channel width. In particular, this is a method for manufacturing an MIS type semiconductor device having a highly doped diffusion layer of the same conductivity type as the substrate.

Effect of the Invention The present invention uses the above-described apparatus and manufacturing method to control the width of the sidewall insulating film so that the substrate can be formed in the upper part of the side surface of the substrate in contact with the groove and in contact with the surface of the substrate, regardless of the channel width. By having a highly doped diffusion layer of the same conductivity type, excessive sidewall current and back gate bias effects are improved. Further, according to the manufacturing method described above, the channel stop at the bottom of the groove-shaped insulating isolation layer and the impurity implantation at the side surface of the substrate in contact with the groove are performed in separate steps. Furthermore, the above manufacturing method eliminates the need for techniques for controlling the tilt angle and impurity implantation angle, which are difficult in terms of process, and can be manufactured using easy manufacturing techniques.

Embodiment FIG. 1 shows an embodiment of a semiconductor device and its manufacturing method according to the present invention in the order of steps. An n-channel MOS transistor will be explained as an example. FIGS. 1(a) to 1(0) are cross-sectional views taken in the direction of channel 1.

(a) P-type silicon substrate 1 with (100) plane
After forming an insulating film 2 with a thickness of 1.3 μm thereon, a photoresist 3 is formed on the insulating film 2 to form a convex insulating film.

(b) Using a photoresist 3, the insulating film 2 is 1.
After etching the convex insulating film 4 by 16 μm, boron 5 was etched at a dose of 2.0×10 13 cIII-2.
A high concentration P+ region 6 is formed by implanting at 0° and an energy of 80 ke. This is the first point of the present invention. This region 6 can reduce excessive sidewall current.

(0) An insulating film is deposited on both side walls of the convex portion of the convex insulating film 4 to a desired thickness and then removed by etching to form a sidewall insulating film 7. The width of the formed sidewall insulating film 7 is assumed to be . The channel width W is 2 times the width of the mask 3.
This is the addition of double Ls. Now Ls is assumed to be 0.06 μm.

(d) Using the convex insulating film 4 and the sidewall insulating film 7 as masks, etching is performed to form a groove 8 with a depth of about 0.6 μm in the silicon substrate 1. This is the second point of the present invention. Poron 9 at a dose of 1.0X10-1”IIg
is implanted with oo and energy 26 to form a channel stop region 1o at the bottom of the groove 8. This is the third point of the present invention.

(e) The insulating film 4 and the sidewall insulating film 7 are removed, and a silicon oxide film 1 is formed in the trench 8 to a thickness that is approximately the same as the depth of the trench.
1 is deposited by CVD method.

Dose amount 4. OX 10・12Ql' (D boron 12
was injected with 0.0 and energy of 40 ke to form 13 regions with 7 blades, and then the region 13 portion + 7 was injected using a well-known method.
) Substrate 1cM OS ) Form a transistor.

As described above, according to this embodiment, the poron high concentration region is all formed in a separate process, so it is easy to set conditions. Moreover, the Porro/high concentration region, which is the key point of the tube 1 of the present invention, can be controlled by L3, the thickness of the insulating film, and the implantation energy, and the sidewall current can be suppressed even for those with a small channel width. Furthermore, since no high boron concentration region is formed on the entire side surface in contact with the groove, the bag gate bias effect can be suppressed. Another feature of the present invention is that the manufacturing process is easy.

6(IL)-((1) shows the channel width of the device according to the present invention and the trench type isolation layer structure with oblique impurity implantation; 1.
These are the results of a simulation of the Poron profile of an n-channel MO8FIET with 6μ theory. Illustration of the conventional method (IL
) and (0), when the channel width becomes small, a high concentration layer is formed over the entire substrate, but in (b) to (+1) according to the method of the present invention, even if the channel width is small, a high concentration P+ layer is formed. Separated.

As described in detail, according to the present invention, channel stop formation, which was conventionally performed in the same process, can be made into an independent process using easy manufacturing technology, suppressing the back gate bias effect, and reducing sidewall insulating film formation. By controlling the weir, even if the channel width is small, a highly concentrated layer of the same conductivity type as the substrate can be formed only on the sidewalls, and excessive sidewall current can be suppressed, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a substrate for an MIS type semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a substrate for an MIS type semiconductor device according to an embodiment of the present invention. 3 and 4 are cross-sectional views of a substrate having a conventional structure, and FIG. 6 is a diagram showing boron profiles of MO8FXT of the present invention and a conventional MO8FXT. 1... P-type silicon substrate, 2... Insulating film 1.3... Photoresist, 4... Convex insulating film, 5...・Poron, 6... P+ region, 7... Side wall insulating film, 8... Groove, 9
...Boro/, 10...Channel stop region, 11...Silicon oxide film, 12...
...Poron, 13...7 control area. Name of agent: Patent attorney Toshio Nakao and 1 other person10
--- Channels 7゜to (t. Figure 2 k ''''--C'lC') Q-to method

Claims (3)

[Claims] (1) A groove-type insulating separation layer with a predetermined depth is formed on one semiconductor substrate, and a part of the upper part of the side surface of the substrate that is in contact with the groove-type insulating separation layer and in a substrate region that is in contact with the substrate surface is formed with the substrate. An MIS type semiconductor device having diffusion layers with different concentrations. (2) The MIS type semiconductor device according to claim 1, wherein the diffusion layer has the same conductivity type as the substrate and has a high concentration. (3) a first step of forming a convex insulating film on one semiconductor substrate; a second step of ion-implanting impurities of the same conductivity type as the substrate using the insulating film as a mask; a third step of forming a sidewall insulating film on both side walls of a convex portion of the insulating film; and a fourth step of etching the substrate to form a groove using the insulating film and the sidewall insulating film as a mask. A method for manufacturing an MIS type semiconductor device.