JPH01107576A - Field effect transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a structure suitable for high frequency operation using a compound semiconductor and a method for manufacturing the same.

(Prior Art) A Schottky barrier gate field effect transistor using a compound semiconductor 9, for example, GaAs, is being put into practical use as a high frequency transistor by taking advantage of the high electron mobility of GaAs. Also, in recent years, field effect transistors that utilize heterojunction interfaces have attracted attention because of their greater high speed performance. Basically, the structure of any of these transistors is as shown in FIG.
A source electrode 1035 and a drain electrode 103D that are in ohmic contact are provided on the n-type GaAs active layer, respectively, and a Schottky gate metal electrode 103G is connected to the n-type GaAs active layer 102.
It is provided on the upper surface of a portion sandwiched between the source electrode 103S and drain electrode 103D.

In the structure described above, due to technical limitations such as photoetching, it is necessary to provide a certain distance between the source and the gate. Therefore, it is necessary to reduce the series resistance by using the n-type GaAs active layer 102, and to reduce the gate length. The performance does not improve as much as expected even with submicronization of the Schottky junction.Furthermore, the properties of the Schottky junction used as the gate structure in the above transistor depend on the surface condition of the semiconductor layer and the formation of the Schottky gate metal electrode 103G. It depends slightly on the method.

The instability of this Schottky junction is directly reflected in the instability of transistor characteristics. Furthermore, since the Schottky junction has a small barrier height and it is difficult to reduce leakage current in the reverse direction, there is a natural limit to the improvement of characteristics when applied to power transistors and the like.

One possible method for improving the drawbacks caused by the Schottky junction is to use a pn junction in the gate structure.

This is shown in FIG. 5, for example.

A p-type region 104 formed by diffusion or ion implantation in an n-type Gan5 operating layer 102 provided on one main surface side of a high resistivity GaAg substrate 101 is connected to a source electrode 1.
03S and the drain electrode 1030, and a gate electrode 103G is formed thereon.

(Problems to be Solved by the Invention) As shown above, this was proposed in order to improve the above-mentioned problems in the field effect transistor with the switch structure shown in FIG. 4.The conventional junction shown in FIG. The type field effect transistor also has the following problems.

That is, when a pn junction is used for the gate.

Compared to a Schottky junction gate, the junction barrier can be made higher, and the instability caused by the metal-semiconductor interface is greatly improved because it is a semiconductor-to-semiconductor junction, and the reverse breakdown voltage is also improved. Furthermore, in the case of a junction field effect transistor formed by a conventional method, the p-type layer 1 formed as a p-type gate region is not improved in any way.
The length (1) of the gate metal electrode 103G is smaller than the length (L) of 04, and the sidewall parasitic capacitance of the gate increases due to the P-type semiconductor layer portion 104a protruding from the gate metal electrode 103G. Therefore, deterioration of the characteristics of the transistor is unavoidable, and therefore it has been difficult to further improve the characteristics of the transistor.

The present invention provides a structure of a junction field effect transistor with excellent high frequency characteristics and a method for manufacturing the same, which is made to eliminate the problems associated with the conventional Schottky barrier gate field effect transistor and pn junction field effect transistor. The purpose is to provide

[Structure of the invention]

(Means for Solving the Problems) A field effect transistor according to the present invention includes an active layer made of an n-type first semiconductor formed on one main surface side of a semiconductor substrate, and an active layer formed on this active layer. a p-type layer made of a second semiconductor having etching characteristics different from that of the first semiconductor formed in the recess, and a pn junction gate made of a metal layer formed on the p-type layer. The manufacturing method thereof includes a step of forming an active layer made of a first semiconductor having at least an n-type surface on one main surface side of the high resistivity semiconductor substrate; a step of forming a recessed portion on the surface of the active layer; a step of laminating a p-type layer made of a second semiconductor having etching characteristics different from that of the first semiconductor on the surface of the active layer within the recessed portion; forming a metal layer on the p-type layer; patterning the metal layer into a desired shape and using this as a mask to selectively remove the p-type layer; It is characterized by being formed.

(Function) In this invention, since the gate electrode is provided in the recessed part, the series resistance of the channel can be reduced, and the gate electrode can be used as a pn
By using a junction, gate stability and gate breakdown voltage can be improved compared to a Schottky junction gate. Further, since this pn junction gate is formed by etching using the gate electrode as a mask, the pn junction region and the gate electrode region have a general shape, and characteristic deterioration due to sidewall capacitance etc. can be greatly reduced.

(Example) Hereinafter, an example of the first aspect of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional view of an InP junction field effect transistor (hereinafter abbreviated as JFET) according to an embodiment of the first invention. In FIG. 1, 1G is a semi-insulating InP substrate; Chloride VPE on the main surface! (Vapor
A buffer layer 11 and an n-type operating layer 12 are formed by continuous vapor phase growth using a phase epitaxial method. Note that it is sufficient that at least the surface of this n-type operating layer 12 is formed to be n-type.

Next, on the n-type operating layer 12, a source electrode 13S and a drain electrode 130 are formed with an AuGe alloy layer and are spaced apart from each other.
A recessed portion 14 is provided in a part of the surface of the n-type operating layer 12 sandwiched between these picture electrodes, and a gate electrode 13G is formed in this recessed portion 14. This gate electrode 13
G is a molecular beam epitaxial method CMBE:Mo1ecula to form a ρ1 junction on the n-type operation M12.
r Beats Epftaxfal)
It consists of a GaAs type semiconductor layer 15a as a lower layer and a Ti metal layer 15b laminated thereon as an upper layer.

Note that each diagonal electrode layer is not limited to the diagonal embodiment, but may be made of a metal that forms ohmic contact with each of the n-type operating layer and the p-type semiconductor layer 15a, and further includes these metals as the bottom layer. It may also have a laminated (two or more layers) structure.

Next, an embodiment of the JFET manufacturing method according to the second invention will be described with reference to FIGS. 2A to 2C, which are cross-sectional views shown in the order of steps.

First, as shown in FIG. 2a, a buffer layer 11 with a donor density of 10"all-" or less is formed on a semi-insulating InP substrate 10 with a donor density of about 1 μm and a donor density of 1.5×10170 m-3.
An n-type active layer 12 of 0.45 .mu.m is grown in a continuous vapor phase by chloride VPE, and then a recess 14 with a depth of about 0.2 .mu.m is formed in the active layer 12 by an ordinary photoetching process.

Next, as shown in Figure 2, MBE is applied to the entire surface of this substrate.
According to the method, the acceptor density is 2 x 10” CI+-”
A high concentration p-type GaAs layer 15a is grown to a thickness of 800 layers.

Subsequently, Au/Pt with a gate length of 1 μm was formed using the lift-off method.
A metal electrode 15b having a laminated structure of /Ti is formed, and using this as a mask, reactive ion etching (RIE) using CHF and gas is performed.
Using the difference in etching rate between GaAs and InP, only the p-type layer other than the gate electrode portion is removed by the etching method to obtain a structure as shown in FIG. 2C. Thereafter, an AuGe-Ni stacked structure is further formed by vapor deposition and lift-off, and an alloying treatment is performed to form a source electrode 13S and a drain electrode 130, thereby obtaining the JFET shown in FIG.

The depressigon field effect transistor obtained by the diagonal method showed high performance with a mutual conductance of 200 m5/mm or more, and good high frequency characteristics.

Although the active layer 12 is formed by the chloride VPE method in the manufacturing method of the diagonal example, it may also be formed by other methods 1, for example, by ion implantation of Si. is formed by metal organic chemical vapor deposition (MOCVD) instead of MBIIE method.
nicChemical Vapor Deposit
(on method).

Furthermore, in the step of etching the lower pfJGaAsJg 15a using the Ti metal layer 15b in the gate electrode as a mask, the lower n-type layer 12 and the removed P
It is important to use selective etching with respect to the mold layer 15a, and therefore, the purpose is not limited to the RIE method, but can also be achieved by wet etching.

In the embodiment described above, the RIE method was used to avoid excessive side etching of the lower p-type GaAs layer 15a in the gate electrode 13G.

Furthermore, in the above embodiment, the n-type active layer 12 is made of an InP semiconductor and the p-type layer 15a is made of a GaAs semiconductor. , ,4. It is clear from the above description that an As layer may be used, and an InP semiconductor layer or, in some cases, a GaAs semiconductor layer may be used as the p-type layer 15a.

Next, the present invention can also be applied to a structure having a heterojunction interface, which will be explained with reference to FIG. That is, in the JFET shown in FIG. 3, 20 is a semi-insulating GaAs substrate, 21 is
is a GaAs layer not doped with impurities.

22 is an n-type AlGaA11 layer, 23 is this AlGaAs
A recess portion formed in the layer 22, 24b is a p-type GaAs layer, and 24a is a gate electrode metal portion formed on the upper surface of this p-type GaAs layer 24b.

24S is a source electrode, and 24D is a drain electrode. This JFET has a pn junction gate 24G consisting of the gate electrode metal part 24a and an underlying p-type GaAs layer 24b.
The two-dimensional electronic layer 25 is controlled to perform a transistor operation, and exhibits extremely excellent characteristics as a low-noise element.

The manufacturing method of this JFET is different from the manufacturing method of the previous example.
An n-type AlGaAs layer 22 is formed on a semi-insulating GaAs substrate 20.
The only difference is in the process of growing a crystal having a heterojunction with the top layer as the top layer using the MBH method or MOCVD method (corresponding to Figure 2 a). There is no change in n-type InP in the second embodiment.
The relationship between the layer 12 and the P-type GaAs layer 15a is
The process may proceed by replacing the relationship between the As layer 22 and the p-type GaAs layer 24b.

〔Effect of the invention〕

As described above, according to the present invention, the channel series resistance can be reduced by etching the underlying P-type layer using the gate electrode metal as a mask to form a pn junction gate within the recessed structure, resulting in a good gate breakdown voltage. A stable JFET can be provided. In addition, as is clear from the gate formation process described above, the pn junction region and gate electrode do not require a mask alignment process and are automatically formed as a stacked structure, which reduces variations in gate breakdown voltage and improves FET characteristics. The uniformity and reproducibility are also improved, which has a significant effect on improving productivity. Furthermore, since the misalignment between the pn-type junction region and the metal electrode is suppressed to a very small level, gate sidewall capacitance is reduced, making it possible to further improve device characteristics.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a pn junction gate type field effect transistor according to an embodiment of the present invention, and FIGS. 2A to 2C show a method for manufacturing a pn junction gate type field effect transistor according to an embodiment of the present invention in order of steps. 3 is a sectional view of a pn junction field effect transistor using a heterojunction according to another embodiment. FIG. 4 is a sectional view of a conventional Schottky barrier gate field effect transistor. FIG. 5 is a sectional view of a conventional Schottky barrier gate field effect transistor. is the conventional p
FIG. 2 is a cross-sectional view of an n-junction field effect transistor. 1o------1---Semi-insulating InP substrate 11---
-------Buffer layer 12, 22---1---N-type operating layer 13S, 24S----Source electrode 130, 24D---Drain electrode 13G, 24G---Gate electrode 14, 23---Recessed part

Claims (2)

[Claims] (1) An active layer made of an n-type first semiconductor formed on one main surface side of a semiconductor substrate, a recess formed in this active layer, and the first semiconductor formed in this recess. A field effect transistor comprising a p-type layer made of a second semiconductor having different etching characteristics and a pn junction gate made of a metal layer formed on the p-type layer. (2) A step of forming an active layer made of a first semiconductor having at least an n-type surface on one main surface side of a high resistivity semiconductor substrate, and a step of forming a recessed portion on the surface of the active layer. a step of laminating a p-type layer made of a second semiconductor having etching characteristics different from that of the first semiconductor on the surface of the active layer in the recessed portion; and a step of forming a metal layer on the p-type layer. , manufacturing a field effect transistor, comprising a step of patterning the metal layer into a desired shape and selectively removing the p-type layer using this as a mask, and forming a pn junction gate in the recess portion. Method.