JPH01110760A - Bicmos semiconductor device - Google Patents

Abstract

PURPOSE:To impose little strain on the input/out resistance in the exchange of signals between the digital circuit section and an analog circuit section and to allow as many processes as possible to be commonly utilized in the manufacture of both bipolar and CMOS circuits by a method wherein source.drain layers are designed to be of a double diffusion structure in at least some of the MOS transistors. CONSTITUTION:In a semiconductor device wherein bipolar transistors and MOS transistors are incorporated into one and the same semiconductor substrate, the source.drain layers of some MOS transistors 51 and 52 out of the n-channel and p-channel MOS transistors are designed to be of a double diffusion structure composed of outer layers 12 and 23 and inner layers 33 and 35. It is so designed that a process of diffusion into the outer layers 12 and 23 is accomplished simultaneously with, and similar in the resultant depth and concentration to, a process of diffusion into semiconductor layers 11 and 21, same as the layers 12 and 23 in conductivity type, of a bipolar transistor 41. This design improves on MOS transistors in terms of their breakdown strength. Such MOS transistors are combined with bipolar transistors for the construction of an analog circuit quite high in input resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a BiCMOS semiconductor device, that is, a semiconductor device in which a bipolar transistor and a MOS transistor are fabricated within the same semiconductor substrate.

[Conventional technology]

The BiCMOS semiconductor device mentioned above, especially the integrated circuit device,
It is suitable for applications where the CMO3 circuit section performs complex processing or calculations on digital signals and data, and then the bipolar circuit section drives an external circuit under desired voltage and current conditions based on the processed signal. CM
Compared to configuring both O3 and bipolar circuit sections as separate semiconductor devices, the entire circuit device can be made smaller and more economical, and the effort of interconnecting both circuit sections after mounting can be saved. Therefore, in recent years, its practical application has been actively promoted and it has come to be used heavily in various applications.

In designing and manufacturing this B iCMO3 semiconductor device, since there are already established technologies and practices for the bipolar circuit section and the CMO3 circuit section, it is natural to use them as they are. In other words, the semiconductor layers fabricated in both types of semiconductor circuit sections have impurity doping concentrations and depths that are passed through each circuit, and these optimum values are unlikely to change the current for both circuits. Although it is built into the same semiconductor substrate, it is bipolar.

CMO3 circuits The two circuits are often designed differently and manufactured through different processes.For example, bipolar circuits are usually used as analog circuits, which require high voltage resistance. Therefore, by increasing the diffusion depth of the base layer or emitter to 2 to 3 am, the breakdown voltage between the collector and emitter can be increased.

On the other hand, CMO3 circuits are of course used as digital circuits, and for this purpose, high-speed operation is required above all else, so although the withstand voltage is low, the diffusion of the source and drain (hereinafter referred to as source and drain in the present invention) layers is required. The depth is set to be quite shallow at 0.2 to 0.8 tna, and the doping concentration of impurities thereto is also set to be relatively high.

[Problem that the invention seeks to solve]

As mentioned above, in the B i CMO3 semiconductor device, the C
The bipolar circuit section often receives the digital signal output from the MO3 circuit section and performs an analog operation based on the digital signal, and therefore it is desirable to smoothly transfer signals between the two circuit sections.

As is well known, MOS transistors have the advantage of high input resistance, but they also have the problem of generally high input resistance, while bipolar transistors have the advantage of low output resistance, but also have the problem of low input resistance. Since there is, Bi
CMOS circuits inherently have the problem that bipolar transistors with low input resistance must be driven by MOS transistors with high output resistance. One way to solve this problem is to use a MOS' transistor designed or configured to have as low an output resistance as possible as the first stage transistor in the analog circuit section, thereby increasing the input resistance to digital signals. B
Since the MOS transistors incorporated in iCMOS semiconductor devices usually have a low breakdown voltage, they cannot be incorporated as is into analog circuits that normally operate under voltages about 10 times higher.

Another problem with conventional BiCMOS semiconductor devices is that the bipolar circuit section and C
The process for the MOS circuit section is done almost separately, except for some basic processes, and this inevitably increases the number of processes and increases the manufacturing cost (this is a common problem). Even if we try to solve this problem and make the processes for both circuit parts as common as possible, it will be impossible unless the design is redesigned so that the diffusion concentration and depth of the semiconductor layers that make up the bipolar transistor and the MOS transistor are the same. As mentioned above, each transistor design has its own meaning and necessity, so it is not possible to redesign it so easily.

The present invention solves the above-mentioned problems, so that the signal reception between the digital circuit section and the analog circuit section can be carried out without any problem with respect to input/output resistance, and in this case, the signal reception between the digital circuit section and the analog circuit section can be made evenly with respect to the input/output resistance. The object or problem is to obtain a BiCMOS semiconductor device in which the steps can be made as common as possible.

[Means for Solving the Problems] The present invention provides for at least some of the n-channel and p-channel MO3 transistors included in the B i CMO3 semiconductor device to have source/drain layers of the MO3 transistors separated by an outer layer and an inner layer. The diffusion into the outer source/drain layer in the double-diffused source/drain layer is performed at the same time and at the same concentration and depth as the diffusion into the semiconductor layer having the same conductivity type as that of the bipolar transistor. By doing so, we succeeded in achieving the above objectives.

[Effect]

The double diffusion structure for the source and drain layers of the MOS (MOS) run raster described above is intended to improve the withstand voltage of the MOS transistor compared to the conventional one, so that it can be used as the first stage of a bi-polar transistor or the first stage of an analog circuit section. By making the diffusion depth of the outer source/drain layer several times deeper than that of a conventional source/drain layer, the breakdown voltage of a MOS transistor is normally 6 to 7V, and the breakdown voltage of a bipolar transistor is 50-100V.
This can be improved by almost an order of magnitude to the level of V.

Further, the impurity diffusion concentration of the outer source/drain layer does not need to be as high as that of the inner source/drain layer, but rather it is advantageous to make it considerably lower than that of the source/drain layer in order to improve its breakdown voltage value.

In this way, the diffusion process suitable for the outer source/drain layer is deeper and has a lower impurity diffusion concentration than the inner source/drain, that is, the normal source/drain. The process is made common to the diffusion process for semiconductor layers for bipolar transistors to streamline manufacturing. of course,
To make this common, the conductivity type of the outer source/drain and the conductivity type of the semiconductor layer of the bipolar transistor must be the same as in the above structure, but fortunately both the n-type and p-type required for the outer source/drain are bipolar. It is included in the semiconductor layer of the transistor, and the diffusion process can be shared with the semiconductor layer for bipolar transistors for the outer source and drain of any conductivity type.For example, when the bipolar transistor is a vertical npn transistor, the p-channel The diffusion of the outer source/drain layer of the MO3 transistor can be shared with the diffusion of the base layer of the bipolar transistor, and the diffusion of the outer source/drain layer of the n-channel MO3 transistor can be shared with the diffusion of the emitter layer of the bipolar transistor.

Furthermore, when the bipolar transistor is a horizontal pnl) transistor, the diffusion of the outer source/drain layer of the p-channel MO3 transistor is the diffusion of the collector layer and emitter layer of the bipolar transistor, and the diffusion of the outer source/drain of the n-channel MOS transistor. can be shared with the diffusion of the Vt layer in contact with the base of a bipolar transistor.

As described above, according to the present invention, the source of the double diffusion structure
The input resistance to digital signals can be increased by using a MOS transistor whose breakdown voltage has been improved by the drain in the front stage of a bipolar transistor, and the diffusion of the source/drain to the outer source/drain layer of the double diffusion structure can be made bipolar. This can be used in common with diffusion into a semiconductor layer for a transistor, thereby solving the above-mentioned problem.

(Example) Hereinafter, the present invention will be described in detail with reference to the figures. Figure 0 shows a partially enlarged cross section of a BiCMOS semiconductor device according to an example of the present invention according to the manufacturing process.
The other part is shown in almost complete condition.

(a) in the figure shows the state at the end of the preparation process, so to speak. A p-type wafer with a specific resistance of about 2 to 3 Ω1 is used as the substrate 1. First, a buried diffusion layer 2 of several depths from the surface is diffused with a strong n-type, and then, for example, 1015 atoms are diffused. An n-type epitaxial layer 113 having an impurity concentration of about /- is grown to a thickness of 7 to 10p. Next, the Hfil region 4 is strongly p-type and deeply diffused from the surface of the epitaxial layer 3 to the substrate 1, and the epitaxial layer 3 is divided into a partial region where the bipolar transistor 41 on the left side of the figure is formed and a MOS transistor on the right side of the figure. 5
1 to 54 are joined and separated into partial regions in which parts 1 to 54 are formed.

The epitaxial middle layer 3 isolated as the left partial region of this layer becomes the collector layer of the bipolar transistor 4I. Furthermore, in the partial region of the epitaxial layer on the right side, n
The p-type well layer 5 for channel MOS transistors 52 and 54 and the n-type well M6 for p-channel MOS transistors 51 and 53 are sequentially connected to IQIS, lQ.
Impurity concentration of about 3 to 5 I & atoms/d! Preparation for fabricating bipolar transistors and MO3 transistors is completed with 0 or more diffused to a depth of m.

In the process shown in (in the figure), the base 1111 of the vertical npn bipolar transistor 41 and the outer source/drain j for the double diffusion structure of the p channel MOS transistor 51 are
W12 is simultaneously diffused in p-type to a depth of 2 to 3-. By setting the impurity concentration at this time to lQl&atom/-, which is suitable for the base layer of a bipolar transistor, it becomes a suitable value also for the outer source/drain layer. In addition, by making the diffusion depth considerably large for an MO-3 transistor as shown above, the p-channel M
It is possible to provide the O3 transistor 51 with a high breakdown voltage value comparable to that of a bipolar transistor. When manufacturing a horizontal pnp transistor on the same semiconductor substrate, the collector layer and emitter layer of the bipolar transistor 41 are also diffused in p-type at the same time in the step shown in (c) of the zero-order diagram. Emitter layer 21
At the same time as the collector connection layer 22, the outer source/drain 7123 for the double diffusion structure of the n-channel MOS transistor 52 is formed with a relatively strong emitter shape of 1.5 to 2.5 μm.
spread to a depth of The impurity concentration at this time is determined by the role of the emitter layer of the bipolar transistor and the impurity concentration of MO3.
The diffusion of the semiconductor layer for the bipolar transistor 41 is completed at 0 or more, which is preferably on the order of 10'' atoms/d so as to pass through both the outer source and drain layers of the transistor.

In order to achieve the final state shown in (d) in the figure, it is necessary to finish the diffusion of the MO3 transistor section, but before that, each MO3
After forming a thin gate oxide film 31 on the surfaces of the portions that will become the channels of the transistors 51 to 54, a polysilicon gate 32 is grown in the usual manner.

p-channel MOS transistor 51.53 p-type source/drain 33.34 and n-channel MOS transistor 52.54 n-type source/drain 35°3
In each case, impurities are implanted by an ion implantation method using the gate 32 as a self-lining mask as usual.

As a result, p-type source and drain 3 are simultaneously diffused.
The source/drain 33 for the double diffused structure MOS transistor 51 in 3.34 and the double diffused structure MOS in the n-type source/drain 35 and 36 which are similarly diffused together.
The source/drain 35 for the third transistor 52 is an inner source/drain and is formed inside the outer source/drain layer 12. In order to shorten the operation time of these double-diffused MO3 transistors as much as possible, it is desirable that the width of these source/drain 33 to
It is appropriate that the diffusion depth of all 36 is approximately 0.5 tna.

The bipolar transistor 41 configured as described above has a high withstand voltage like the conventional one, and has the same performance as the conventional one in terms of current amplifier characteristics. Although it has a low breakdown voltage, it also has high-speed operation performance.

On the other hand, the p-channel MOS transistor 51 and the n-channel MO3 transistor 52, which have a double-diffused source and drain structure, are slightly inferior to the normal MOS transistors 53 and 54 in terms of operating speed, but compared to the bipolar transistor 41. It can be provided with comparable high breakdown voltage performance, and has a high human resistance value similar to that of a normal MO3 transistor suitable for use as a front-stage transistor such as the bipolar transistor 41. Of course, the output resistance is determined by the design of the channel of the MO3 transistor 51, 52, and by appropriately selecting the dimensions of the channel, that is, the length and mutual spacing of the source and drain, the output resistance value that leads to coupling with the bipolar transistor can be determined. You can have it. By forming the source/drain into a double diffusion structure, the dimensions of the MO3 transistor do not become particularly large; rather, the dimensions are influenced by the selection of the output resistance value.

These high-voltage MO3 transistors 51 and 52 are suitable as input transistors of, for example, an operational amplifier or a differential amplifier due to their high input resistance. Conventionally, Darling transistors have often been used as the input transistors of these amplifiers, but in cases where a special high gain is required, this can be replaced with the high voltage MOS transistor according to the present invention and an ordinary bipolar transistor. It is also possible to construct an amplifier with significantly higher input resistance.

Note that in the above embodiment, M in the BiCMOS semiconductor device
Although we have shown an example of incorporating both a high voltage MO3 transistor with a double diffused source/drain structure as an OS transistor and a conventional MOS transistor with low voltage resistance and high operating speed, it is possible to use a B i CMO3 semiconductor device as needed. Of course, it is also possible to dedicate the circuit to an analog circuit, so to speak, and incorporate only high voltage MOS transistors and bipolar transistors into it.

〔Effect of the invention〕

As described above, according to the present invention, n-channel and p-channel MO
For at least part of the three transistors, the source/drain layer of the Tomi MO3 transistor has a double diffusion structure consisting of an outer layer and an inner layer, and the diffusion to the outer source/drain layer in the double diffused source/drain layer is By simultaneously diffusing into a semiconductor layer having the same conductivity type as that of a bipolar transistor and at the same concentration and depth, M with a source/drain having a double diffusion structure
Since the breakdown voltage value of the OS transistor can be improved by approximately one order of magnitude compared to the conventional one, by combining this with a bipolar transistor, it becomes possible to create an analog circuit with a much higher input resistance than the conventional one in the B i CMO3 semiconductor device. Furthermore, the main parts of the diffusion process for the MOS transistor and the bipolar transistor can be shared, thereby streamlining the manufacturing process of the BiCMOS semiconductor device.

These advantages of the present invention are particularly useful for incorporating high operating speed digital circuits and analog circuits such as operational amplifiers with high input resistance into BiCMOS integrated circuit devices, thereby further improving the performance of BiCMOS semiconductor devices. It is expected that this technology will contribute to its development and expansion of applications.

[Brief explanation of the drawing]

The figure is a partially enlarged sectional view showing each main manufacturing process of an embodiment of a BiCMOS semiconductor device according to the present invention. In the figure, 1: substrate, 2: buried diffusion layer, 3: epitaxial layer, 4
: separation region, 5.6: well layer, 11: base layer, 12
: Outer source/drain layer, 21: Emitter layer, 22:
base connection], 23: outer source/drain layer, 31:
Gate oxide film, 32: Gate, 33, 35: Inner source/drain layer, 34, 36: Source/drain, 41:
Vertical epitaxial bipolar transistor, 51:
p-channel MO with double diffused source and drain structure
S transistor, 52: n-channel MOS transistor with double-diffused source and drain structure, 53: p-channel MOS transistor, 54: n-channel MO3 transistor, procedure correction manual) 6312 @ % formula %: 1, Incident display Tokutonsho/λ-/ri? ρλL3, Relationship with the case of the person making the amendment Address of the person making the amendment 1-1 Tanabeshinden, Kawasaki-ku, Kawasaki City Name +
52J Fuji Electric Co., Ltd. 4, Agent Address: 1-1 Tanabeshinden, Kawasaki-ku, Kawasaki City On page 17, line 2 of the amended statement of contents, Figure 1 says "j", whereas Figure 1 says "j". and correct it.

Claims (1)

[Claims] 1) A semiconductor device in which a bipolar transistor and a MOS transistor are fabricated in the same semiconductor substrate,
For at least some of the n-channel and p-channel MOS transistors, the source/drain layers of the MOS transistors have a double-diffused structure consisting of an outer layer and an inner layer, and the outer source/drain layers in the double-diffused source/drain layers A BiCMOS semiconductor device characterized in that diffusion into a drain layer is performed simultaneously with diffusion into a semiconductor layer having the same conductivity type as that of a bipolar transistor and at the same concentration and depth. 2) In the semiconductor device according to claim 1,
A BiCMOS semiconductor device characterized in that diffusion into the outer source/drain layer of a MOS transistor is simultaneously performed on a base layer or an emitter layer having the same conductivity type as that of a vertical bipolar transistor. 3) In the semiconductor device according to claim 1,
A BiCMOS semiconductor device characterized in that diffusion into the outer source/drain layer of a MOS transistor is performed simultaneously with a collector layer and an emitter layer or a base connection layer having the same conductivity type as that of a lateral bipolar transistor.