JPH01111348U - - Google Patents
Info
- Publication number
- JPH01111348U JPH01111348U JP670488U JP670488U JPH01111348U JP H01111348 U JPH01111348 U JP H01111348U JP 670488 U JP670488 U JP 670488U JP 670488 U JP670488 U JP 670488U JP H01111348 U JPH01111348 U JP H01111348U
- Authority
- JP
- Japan
- Prior art keywords
- section
- serial transfer
- cpu
- status
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012806 monitoring device Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Information Transfer Systems (AREA)
- Debugging And Monitoring (AREA)
Description
第１図はこの考案によるシリアル転送動作監視
装置の一実施例の全体構成図、第２図はこの考案
のコード表示制御部及びコード表示部の詳細な構
成図、第３図は従来のシリアル転送の構成図であ
る。
図において１はＣＰＵ部、２はシリアル転送部
、３はステータス表示部、４はコントロール信号
、５はアドレス信号、６はデータ信号、７はシリ
アル・データ信号、８は入出力計数部、９は表示
部、１０はアドレスデコード回路、１１は読みと
りゲート回路、１２は書き込みゲート回路、１３
Ａ，１３Ｂはカウンタ回路、１４Ａ，１４Ｂは表
示回路である。なお、図中同一あるいは相当部分
には同一符号を付して示してある。
FIG. 1 is an overall configuration diagram of an embodiment of the serial transfer operation monitoring device according to this invention, FIG. 2 is a detailed configuration diagram of the code display control section and code display section of this invention, and FIG. 3 is a diagram of the conventional serial transfer operation monitoring device. FIG. In the figure, 1 is a CPU section, 2 is a serial transfer section, 3 is a status display section, 4 is a control signal, 5 is an address signal, 6 is a data signal, 7 is a serial data signal, 8 is an input/output counter, and 9 is a Display section, 10 is an address decoding circuit, 11 is a read gate circuit, 12 is a write gate circuit, 13
A and 13B are counter circuits, and 14A and 14B are display circuits. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.
Claims (1)
ｇ Ｕｎｉｔ）部と、ＣＰＵ部の制御に基づきシ
リアル転送を行なうシリアル転送部と、ＣＰＵ部
がシリアル転送部にデータを書き込む回数と読み
出す回数を計数する入出力計数部と、入出力計数
部の出力を表示する表示部と、シリアル転送部の
ステータスを表示するステータス表示部をシリア
ル転送の送信側と受信側にそれぞれ備えているこ
とを特徴とするシリアル転送監視装置。 CPU
g Unit) section, a serial transfer section that performs serial transfer based on the control of the CPU section, an input/output counter section that counts the number of times the CPU section writes and reads data to the serial transfer section, and an output of the input/output counter section. 1. A serial transfer monitoring device comprising: a display section that displays the status of the serial transfer section; and a status display section that displays the status of the serial transfer section on the transmitting side and the receiving side of the serial transfer, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP670488U JPH01111348U (en) | 1988-01-22 | 1988-01-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP670488U JPH01111348U (en) | 1988-01-22 | 1988-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01111348U true JPH01111348U (en) | 1989-07-27 |
Family
ID=31211093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP670488U Pending JPH01111348U (en) | 1988-01-22 | 1988-01-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01111348U (en) |
-
1988
- 1988-01-22 JP JP670488U patent/JPH01111348U/ja active Pending
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