JPH01112180A - Self-test circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to self-test circuits in digital circuits, which allow users to test their functionality by themselves.

The conventional technology self-test circuit is a circuit under test (CUT (C1rc)).
It consists of a pattern generator that generates a test pattern for the pattern (denoted as UIT UNDER TE5t), an analyzer that analyzes the output of the CUT for this pattern, or a comparator and test control circuit that compares and compares it with an expected value.

As the test pattern, a random pattern with a high failure detection rate is better used than a regular pattern generated by a counter. The second random pattern generator
A linear feedback shift register (
Hereinafter referred to as LFSR), in this case the generation function is f(
x)=x4+x3+1, and has a length of 4 bits as shown in Figure 3 (Q3, Q2, Ql, Qo,)
= All combination patterns other than (0,0,0,0) (
15 types) are initialized to (1, o, o, o) with pseudo 3/\-no, and “INT” is set to
Pattern generation can be executed from then on by returning the signal to the normal level and applying the clock CLK. In clock synchronous CUT,
There is a flip-flop (so-called register) in the input section that takes in the input signal in synchronization with the clock.
FIG. 4 shows a circuit in which this register is used as an LFSR so that it can also be used as a pseudo-random pattern generator.

If the "T E S T '" signal is set to "L", the circuit operates as a 4-bit input register (normal operation mode). If the "T E S T " signal is set to "H", this circuit operates as a 4-bit LFSR. A pattern is generated for the CUT (test mode).

The response to the test pattern of the CUT is processed by an analyzer or comparator, and a parallel signature analyzer as shown in FIG. 5 is used as a divider for the parallel outputs (Z3.Z2.Zl, Zo) from the CUT. Among the division results of the parallel outputs, the remainder of the quotient is left in the flip-flop as a signature, and by comparing the result with the expected value, it is possible to judge whether the CUT is good or bad. The signature obtained by the parallel signature analyzer must be transferred to a comparator for comparison with the expected value.

A BILBO shown in FIG. 6 is a circuit having both signature generation and transfer functions.

(Koneman, B., etal, “Bui
lt-InLogicBlock 0bservati
on Technique, ” Dig, , 197
9 I, I, I, I, Test Conference (I E
EETest Conf, ), pp, 3-41, O
ct, 23-25° 1979,) BILBO has two control lines B1 and B2, and four operating modes can be selected. (B1.B2)-(0,0
), all flip-flops are initialized to "O" in synchronization with the clock.

At (0,1), it operates as a shift register, and "5c
The data serially read from the "an in" terminal is shifted and output to the "5 can out" terminal.

At (1,0), it operates as a parallel 4-bit register, and (
In 1, 1), a 4-pint signature is calculated as a parallel 4-bit signature analyzer.

51\-7 A conventional self-test circuit using LFSR and BILBO is shown in FIG. The input section of circuit blocks 1 to 5 has a fourth
The circuits 6 to 10 shown in the figure are configured with the number of bits corresponding to the number of input signals, and the operation of the input register/LFSR is switched by the "TEST"' signal line.

At the output section of the circuit block, B I LB shown in FIG.
O23 to O27 are configured with the number of bits corresponding to the number of output signals, and B1. The operation mode is selected by the control line B2.

Each BILBO is connected in series as shown in FIG. 7 to transfer the calculated signature to the comparator. The test sequence of this self-test circuit will now be described. During normal operation, “T E S T” is set to L.
I+.

Set (B1.B2)=(1, O) and operate CUT+7) The pattern generator in the input section operates as an input register, and the BILBO in the output section operates as an output register.

In test mode, T E S T ” is n H
Set to I+ and input a pseudo random pattern from the input section.
T and sets (B1, B2)=(1, 1) to operate BILBO as a signal to the parallel signature analyzer 6. As a result, a signature for the output of each circuit block is generated and stored in a flip-flop in each BILBO. The generated signature is (B
1, B2) - (0, 1), it is sequentially scanned out to the comparator and can be compared with the expected value.

Problems to be Solved by the Invention In such a conventional self-test circuit, as many BILBOs as there are circuit blocks to be tested are required.
The number of gates (hardware amount) required to configure LF
Compared to SR, the overall hardware overhead increases as the system is much larger. Also, during normal operation, B
The ILBO acts as an output register and latches the output of the circuit block to the flip-flop, but a signal delay equivalent to one gate of two gates is added to the path to the input of the flip-flop.

Means for Solving the Problems The present invention aims to solve the above problems, and each circuit block 7/\-
The output of the Norok is transferred to a plurality of test dedicated buses via a switch, and the signature of the output is calculated using a signature analyzer connected to each of the buses.

Operation The present invention has the above-mentioned configuration, and a signature analyzer (BI).
LBO) to reduce the amount of hardware and improve BI
By separating the LBO from the output signal bus of the circuit block, it is possible to eliminate the signal delay caused by the addition of the circuit.

Embodiment FIG. 1 is a block diagram showing an embodiment of the self-test circuit of the present invention. In FIG. 1, circuit blocks 1 to 5 have input pattern generators 6 to 1Q. The outputs of each circuit block 1 to 6 are controlled by switches 11 to 15,
It is connected to test dedicated buses 16-18. The test dedicated buses 16 to 18 are precharged to enable high-speed operation. In the case of this embodiment, circuit blocks 1 and 4 are connected to the test I/dedicated bus 16, circuit blocks 2 and 5 are connected to the test dedicated bus 17, and circuit block 3 is connected to the test dedicated bus 18.
It is connected to the. Test buses 16 to 18 include B
ILBOs 19 to 21 are connected to each other. The test control circuit 22 performs test mode switching and test sequence control. During normal operation, the test control circuit 22 outputs "T E S T 1" and "T
Set the E S T 2" signal to 11 L" and operate the input pattern generators 6 to 1o as input registers,
Switches 11 to 15 are turned OFF to isolate the test dedicated bus and BILBOs 19 to 21 from the normal operation signal bus.

In this case, test control circuit 22 has no effect on normal operation. During the test, “T E
Set S T 1" to IIH" and 'TEST2' to L" to operate pattern generators 6 to 8, and BILBO1
9 to 21 are set to (B1, B2)=(1, O) and operated in parallel signature analyzer mode. The output for the input pattern of circuit blocks 1 to 5 is switch 1.
Since signals 1 to 13 are turned on, signals 9.\-7 are transferred to test dedicated buses 16 to 17, and BILBOs 19 to 21 calculate the signature for each output. Since the input pattern lengths to circuit blocks 1 to 5 are different, each pattern generator 6 to
When 1o completes one cycle of pattern generation, B
If the signature analyzer operation of ILBO'1 to ILBO'5 is stopped, the signature can be obtained accurately. The obtained signatures are set to (B1, B2) = (0, 1) and transferred in series to the comparator side, and the three signatures are compared with expected values to determine the acceptability of circuit blocks 1 to 3.

For the remaining blocks 4 and 5, "T E S T
1'' to II L II, " T E S T 2
is set to "H" and input patterns are supplied from the pattern generators 9 to 1o, signatures are calculated in the same manner as described above, and are serially transferred. In this way, the five circuit blocks will be subjected to self-tests twice.

In this embodiment, a test-only bus is used, but in a digital circuit (such as a CPU) that originally has an internal bus, that bus can be used during testing.

10-＼ / Effects of the Invention The present invention realizes self-test by verifying the output pattern by combining BILBO and a test bus, and realizing signature analysis of the circuit output with a small increase in the number of gates. , and the number of circuit blocks equal to the number of BILBOO can be tested simultaneously, thereby shortening the test time. Furthermore, since the input pattern is generated by the pattern generator, pattern creation work is no longer necessary. Therefore, the present invention can be said to be an extremely effective circuit for testing large-scale digital systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a self-test circuit according to an embodiment of the present invention, and FIG. 2 is a linear feedback shift register (L
FSR) logic circuit diagram, Figure 3 is an explanatory diagram showing a list of patterns generated by the circuit in Figure 2, Figure 4 is LFS
Logic circuit diagram of a register circuit that can also be used as R, No. 5
6 is a logic circuit diagram of a parallel signature analyzer, FIG. 6 is a logic circuit diagram of a BILBO, and FIG. 7 is an 11/\-7 block diagram of a conventional self-test circuit. 1-5...Circuit block, 6-10...
・L F S R/Register, 11 to 15...
Switch, 16-18... Test dedicated bus, 1
9～21.23～27...BILBo, 22・
...Test control circuit.

Claims (2)

[Claims] (1) An input pattern generator provided at each input section of a circuit divided into a plurality of parts, a switch that connects the circuit output corresponding to the input pattern from the pattern generator to a plurality of buses, and a switch that connects the circuit output corresponding to the input pattern from the pattern generator to the plurality of buses; and a test control circuit that controls the input pattern generator, the switch, and the divider. Self-test circuit. (2) The self-test circuit according to claim 1, which uses a linear feedback shift register (LFSR) as an input pattern generator.