JPH01112341A - Parity checking circuit - Google Patents

Abstract

PURPOSE:To detect the destruction of a data of a memory element to the best even in a bit map memory where bit write is performed by selecting data of 8 bits on which no bit write is performed, and performing parity check. CONSTITUTION:A detecting means 15 detects the data in which all 8 bits are written at the time of writing the data, and stores it in a storage means 16, and the storage means 16 informs the data on which all 8 bits are written and for which correct parity check can be performed to a permission means 17 at the time of reading. Therefore, the permission means 17 sends a result on which the correct parity check is applied to a terminal F via a flip-flop 14. In such a way, it is possible to detect the destruction of the data by the memory device to the best.

Description

[Detailed Description of the Invention] [Summary] A bitmap memory in which multiple bits of data are written and arbitrary bits in a memory area specified by an address for writing the data are rewritten. Regarding the parity check circuit that selects only data that will not be rewritten and performs a parity check, select 8-bit data that will not be rewritten,
The purpose of the parity check is to detect data corruption caused by the memory element as much as possible.The device is equipped with the above-mentioned bitmap memory, and each bit of data is written to each address and each chip of the memory. In a circuit that sends an enable signal to write data or arbitrary bits, and also creates a check bit and performs a parity check, when all the enable signals supplied to the chip are "1", it is "1". ”, a storage means for storing an enable bit corresponding to an address for writing data into the bitmap memory when the detection means sends a “1”, and a storage means for storing an enable bit when reading data from the bitmap memory. , a permission means is provided to permit transmission of the parity check result when data is successively sent out by the address for which three enable bits have been set from the storage means, and any bit among the plurality of bits of the data is not rewritten. The configuration is such that a parity check is performed only when the

[Industrial application field]

The present invention relates to a bitmap memory in which data consisting of a plurality of bits is written and arbitrary bits in a memory area specified by an address for writing the data are rewritten, and in particular, the present invention relates to a bitmap memory in which data consisting of a plurality of bits is written and arbitrary bits in a memory area specified by an address for writing the data are rewritten. The present invention relates to a parity check circuit that selects only data that will not be rewritten and performs a parity check.

To know if data is corrupted in a memory element, create and write a parity check bit when writing data to memory, and when reading data from memory, read the parity check bit of the corresponding data and perform a parity check. It is commonly practiced to do so.

By the way, a bitmap memory for storing graphic data has a focus writing method that rewrites only arbitrary bits without reading out the data written in the memory. That is, when data is written to the memory, it is normally written in units of, for example, 8 bits, but when performing focus writing, only one arbitrary bit among the 8 bits is rewritten.

When such focus writing is performed, a parity check bit is created every 8 bits, so if the read 8-bit data is parity-checked, an error will occur. Therefore, parity check cannot be performed on 8-bit data written in bits.

However, since 8-bit data with no bits written can be checked for parity, it is desirable to select this data and perform a parity check.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a display device.

The processor 1 operates by reading a program stored in the ROM 2, and stores commands and display data input from the host device via the interface circuit 3 in the RAM 4, and then reads them out. The processor 1 that has analyzed the command then develops the display data for one screen in the bitmap memory 5, controls the display control circuit 6 to read out the display data developed in the bitmap memory 5, and displays the display data on the display section 7. to be displayed.

FIG. 4 is a diagram explaining bit writing.

As shown in FIG. 4, the display data developed in the bitmap memory 5 is drawn as a grid. If, for example, X is to be written on this grid, then
When writing, the address sent to write the X is,
It is necessary to read data from the bit map memory 5 in units of, for example, 8 bits, superimpose a bit for writing X on this 8 bit data, and write it into the focus map memory 5 again.

This is because if X is written as is into the bitmap memory 5, the data in the area of the bitmap memory 5 where the 8 bits for writing This is because it will be done. Therefore, it is necessary to access the bitmap memory 5 twice and it takes time, so when writing X, instead of writing in 8-bit units, when writing By rewriting only the bits to be accessed, the bitmap memory 5 can be accessed only once.

FIG. 5 is a block diagram showing an example of a parity check circuit.

FIG. 5 is a detailed block diagram of the bitmap memory 5 of FIG. When writing data to the bitmap memory IO, for example, 8-bit data sent from the processor 1 is input from the terminal A to the receiver 8, and a write signal is input from the terminal B. Therefore, receiver 8 is enabled and sends this 8-bit data to bitmap memory 10 and parity generator 11.

At the same time, the address sent by processor 1 from terminal E is
A write enable signal for each chip constituting the bitmap memory 10 is input from a terminal to the bitmap memory 10 and the parity memory 12, and is supplied to each chip of the bitmap memory 10.

Therefore, 8-bit data is written into the bitmap memory 10, and based on this 8-bit data, the parity generator 11 creates a parity check bit and writes it into the parity memory 12.

When reading data from the bitmap memory 10, an address is input from the processor 1 or the display control circuit 6 via the terminal E, and a read signal is input to the driver 9 via the terminal C.

Therefore, the driver 9 is enabled and transfers the 8-bit data successively output from the bitmap memory 10 to the terminal A.
The 8-bit data simultaneously read from bit map memory 0 is sent to parity memory 12 at the address input from terminal E in parity checker
The parity check bit is checked along with the parity check bit read from the parity check bit.

As a result of the parity check performed by the parity checker 13, if there is a parity error, the flip-flop 14
1'' is sent out.Flip-flop 14 is therefore set by the clock coming from terminal G and sends out a parity error signal to terminal F.

[Problem that the invention seeks to solve]

As described above, the parity check circuit for detecting data corruption caused by the memory elements of the conventional bitmap memory 10 requires, for example, 8-bit units of data to be written to the bitmap memory 10. Therefore, if bits 1 to 7 of these 8 bits are rewritten, the parity checker 13 cannot perform a parity check using the parity check bits written to the parity memory 12. .

This is because a parity error is sent even though there is no data corruption in the memory element. For this reason, there is a problem in that the bitmap memory 10 that performs bit writing cannot perform a parity check.

The present invention selects 8-bit data to which no bit writing is performed and performs a parity check to detect data destruction caused by memory elements as much as possible even in the bitmap memory 10 where bit writing is performed. The purpose is to

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 1 is the same as in FIG. 5, with detection means 15, storage means 16, and permission means 17 added. Bitmap memory 10
When data is written to the bitmap memory 10, the detection means 15 detects that the write enable signal input from the terminal to enable each chip of the bitmap memory 10 is all "do", that is, when all 8 bits of data are written, "l" is sent to the storage means 16 as an enable bit.

If the write enable signal is not "1" in i and e, that is, if a bit is written, the enable bit is not sent to the storage means 16.

The storage means 16 stores this enable bit at the address input from the terminal E.

When data is read from the bitmap memory 10,
Bitmap memory 1 with the address input from terminal E.
Data is read from 0. At this time, the enable bit may or may not be read from the storage means 16. That is, when the data read from the bit map memory 10 is written in 8 pins, the enable bit is read out, and if the data is written in 8 pins, the enable bit is not read out.

The enabling means 17 receives a read signal from the terminal C to instruct data reading, and when the enable bit is read from the storage means 16, the parity checker 1
2 [Operation] With the above configuration, the detection means 15 detects the written data of all 8 bits at the time of data writing and stores it in the storage means 16. When data is read, all 8 bits are written into the storage means 16 to notify the permission means 17 of data for which a correct parity check can be performed. The signal is then sent to terminal F. Therefore, even in the bitmap memory 10 where bit writing is performed, data destruction caused by memory elements can be detected as much as possible.

〔Example〕

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention.

The same reference numerals as in FIG. 5 indicate the same functions. When writing data to the bitmap memory 10, for example, 8-bit data sent from the processor l from the terminal A is sent to the receiver 8.
, and a write signal is manually input from terminal B. Therefore,
Receiver 8 sends this 8-bit data to bitmap memory 10 and parity generator 11.

At the same time, the address sent by the processor 1 from the terminal E is input to the bitmap memory 10, parity memory 12, and enable bit memory 19, and from the terminal E, the write enable signal of each chip constituting the bitmap memory IO is input, and the bit Each chip of map memory 10 and A
The signal is supplied to the ND circuit 18.

Therefore, 8-bit data is written into the bitmap memory 10, and based on this 8-bit data, the parity generator 11 creates a parity check bit and writes it into the parity memory 12.

Since the AND circuit 18 receives a write enable signal for writing all 8 bits into the bitmap memory 10, it sends "1" to the enable bit memory 19.

When focus writing is performed, only the bit for writing is input from terminal A, and a write enable signal for the chip to write the bit is input from terminal A. Therefore,
AND circuit 18 sets “0” to enable bit memory 19
Send to. Therefore, the enable bit memory 19 erases the enable bit at the address where the bit was written.

When reading data from the bitmap memory 10, an address is input from the processor 1 or display control circuit 6 to the bitmap memory 10, parity memory 12, and enable bit memory 19 via terminal E, and a read signal is input via terminal C. Input to driver 9.

Therefore, the driver 9 is enabled and transfers the 8-bit data read from the bitmap memory 10 to the terminal A.
The 8-bit data read out from the bitmap memory 10 at the same time is sent to the parity memory 12 at the parity checker 13 at an address starting from the terminal E.
The parity check bit is checked along with the parity check bit read from the parity check bit.

The address input from terminal E is input to enable bit memory 19, and the contents of enable bit memory 19 are read out. In this case, if the address is a bit written address, the enable bit will not be read. Therefore, A
Since “0” is input to the ND circuit 20, the AND circuit 20
outputs "0", and the AND circuit 21 blocks the output of the parity checker 13, so the flip-flop 14 does not output the parity check result.

When the enable bit is read from the enable bit memory 19, "1" is sent to the AND circuit 20, and A
Since the read signal is input from the terminal C, the ND circuit 20 sends out "1", and the AND circuit 21 sends the output of the parity checker 13 to the flip-flop 14. Therefore, if there is a parity error as a result of the parity check performed by the parity checker 13, the clip flop 14
“1” is sent to Therefore, flip-flop 14
is set by a clock input from terminal G, and sends a parity error signal to terminal F.

〔Effect of the invention〕

As explained above, in the present invention, bit writing is not performed.
Since it is possible to select bit data and perform a parity check, it is possible to detect data destruction caused by memory elements as much as possible even in the bit map memory 10 where bit writing is performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a circuit showing an embodiment of the invention, Fig. 3 is a block diagram showing an example of a display device, and Fig. 4 explains bit writing. FIG. 5 is a block diagram showing an example of a parity check circuit. In the figure, 1 is a bromo sensor, 2 is a ROM, 3 is an interface circuit, 4 is a RAM, 5.10 is a bitmap memory, 6 is a display control circuit, 7 is a display section, 8 is a receiver, 9 is a driver, 11 12 is a parity generator, 12 is a parity memory, 13 is a parity checker, 14 is a flip-flop, 15 is a detection means, 16 is a storage means, 17 is a permission means, and 18, 20, and 21 are AND circuits. ni) - (I-v- ＼ Loli ni agony expression Howaka) My example and Hozu 2' mouth/So 2 illustration 3 n Bi.../To@S Yokku 兇υ Month Riro G co Preliminary 4 [

Claims (1)

[Scope of Claims] A bitmap memory (10) in which data consisting of a plurality of bits is written, and in which arbitrary bits in a memory area indicated by an address for writing the data are rewritten, Sending an address for writing the data into the bitmap memory (10) and sending an enable signal to write each bit of the data to each chip constituting the bitmap memory (10), After writing the data or arbitrary bits and creating a parity check bit for each data, writing the data to the bitmap memory (10) and reading the data from the bitmap memory (10). When the enable signal is supplied to all the chips, a detection means (15) is included in the circuit that reads the parity check bit created for the data and performs a parity check. , the detection means (15
) sends out a detection signal, the bitmap memory (1
storage means (16) for storing an enable bit corresponding to an address at which data is written to bitmap memory (10);
) When the data of the bitmap memory (10) is read by the address that read the enable bit from
Permission means (1) for permitting sending of parity check results
7), and when any bit among the plurality of bits of the data read from the bitmap memory (10) has not been rewritten, the result of the parity check is sent out. parity check circuit.