JPH01112342A - Method for simulating logic circuit - Google Patents

Abstract

PURPOSE:To simultaneously simulate (k) test patterns by providing (k) arithmetic mechanisms. CONSTITUTION:The test patterns (0)-(3) are propagated corresponding to the arithmetic mechanism 20-23, 30-33, and 40-43 of devices, respectively. When the propagation of a logic value of rank 1, the arithmetic operations of device groups 20-23 of rank 2 are performed simultaneously, and it is checked whether or not an event is generated. The output of a changed device is propagated to the devices 30, 32 and 33, and 40, 42 and 43 of the next rank (rank 3), and corresponding model number and logic are propagated at the time of propagation. When the arithmetic operation at the rank 2 is completed, the arithmetic operations of the device groups 30-33 and 40-43 of rank 3 are performed simultaneously, and those computed results are propagated to primary output terminals 50 and 51. In such a way, it is possible to perform the logical simulation of plural test patterns simultaneously.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic circuit simulation method.

[Conventional technology]

Conventionally, logic simulators that perform simulations of this type of logic circuit have been implemented using software or hardware (in fact, one model can only perform one simulation. (For example, Sasaki et al. 17 Mixed Level Simulator for Large Digital System Logic Verification
later for Large Digital S
System Logic Verification)
” 17th DA Conf.

pp. 626-63-3 (1980)) [Problems to be Solved by the Invention] The conventional logic simulator described above stores only one model's worth of data on the simulator, so when it is executed, one model's worth of data is stored. You can only perform operations on Therefore, for C: where many failures must be simulated for the same circuit, such as failure simulation.

The disadvantage is that it takes an extremely large amount of time.

[Means for solving problems]

The logic circuit simulation method according to the present invention uses only one model's worth of data as the elements of two circuits (elements are gates, functional blocks, etc.) and the connection information between the elements.
A maximum of (k≧2) device simulations are executed simultaneously, logic propagation is performed using corresponding model numbers and logic values, and only the device where an event occurs is subject to simulation. do.

In addition, in the second aspect of the present invention, a target model containing connection information is divided into n sub-models, and the n sub-models are executed simultaneously.

Furthermore, in the present invention, elements are ranked from primary input to primary output or from register to register, and execution is performed in units of ranks.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 2, the logic circuit used to explain the simulation method of the present invention includes primary input terminals 1'0, 11, 12 and 16 and primary input terminals 1'0, 11, 12 and 16.
It has output terminals 50 and 51, and elements 20, 30 and 40 constituting a logic circuit are connected between them.

The primary input terminal 10 is connected to the element 3 via the signal line 60.
0, the primary input terminals 11 and 12 are connected to the first and second input terminals of the element 20 via signal lines 61 and 62, respectively, and the primary input terminal 16 is connected to the first and second input terminals of the element 20 via signal lines 61 and 62, respectively. 63 to one input terminal of the element 40. The output terminal of element 20 is connected to the other input terminal of element 30 via signal line 64 and to the other input terminal of element 40 via signal line 65%. The output terminal of the element 30 is connected to the primary output terminal 50 (-) through the signal line 66, and the output terminal of the element 40 is connected to the primary output terminal 51 (-) through the signal line 67.
(=Connected.

The patterns indicated by ■ to ■ on the left side of FIG. 2 are test data (patterns) used when simulating this logic circuit, and the patterns indicated by ■ to ■ on the right side are respectively.

These are Z result data (patterns) showing the results of simulating this logic circuit.

Further, as shown in Figure 9, the ranks are distributed from the primary input terminal to the primary output terminal. That is, primary input terminals 10, 11, 12 and 13 have rank 1, element 20 (2 has rank 2, elements 30 and 40 have rank 3, primary output terminals 50 and 5
1 is assigned rank 4.

FIG. 1 is a diagram for explaining a simulation method according to the present invention. Figure 1 (2.

Element groups 21-23, 31-33 and 41-43 correspond to elements 20, 30 and 40 in FIG. 2, respectively.

Element groups 20 to 23, 30 to 33, and 40 to 46 correspond to element operation C during simulation. In this example, the number of element groups is four (k=4), but this number can be set to any number greater than or equal to two. Therefore, in this example, the four test patterns 1 to 1 shown in FIG. 2 can be simultaneously simulated as described in detail below.

Next (-1 Simulation method according to the present invention (Fig. 1)
So, Figure 2C: The logic circuit shown.

The operation when performing logic simulation using test patterns ■ to ■ will be explained.

1) First, rank 1 primacy input terminals 10 to 16
Test patterns ■～■ are set.

11) These test patterns ■~■ are for signal lines 60~
66 to the arithmetic mechanisms of rank 2 and 6 elements. Test patterns ■ to ■ are as shown in FIG. 3, respectively.

It is transmitted corresponding to the calculation mechanisms 20-23, 30-33, 40-43 of the element.

1ii) When the logical value propagation in rank 1 is completed, calculations are performed on the element groups 20 to 25 in rank 2. This element group 2
Operations 0 to 23 are performed simultaneously. Here, element group 2
Whether the outputs of 0 to 23 have changed compared to the previous state,
In other words, check whether an event has occurred. In the case of this example, if the initial values of the element groups 20 to 23 are 0'',
The elements 20, 22, 23 take on a modified shape. Therefore, the outputs of the elements 20, 22.23 are the elements 30, 32.33 and 40, 42, of the next rank (rank 3), respectively.
Propagates to 43. During propagation, the corresponding model number and logic are passed on.

iv) When the calculation in rank 2 is completed, the calculations in the element groups 30 to 33 and 40 to 43 in rank 6 are performed simultaneously (two times), and the results of these calculations are propagated to the primary output terminal 50.51.

FIG. 3 (- indicates which element arithmetic mechanism (=corresponds to) each pattern at each rank and how the logic is simulated.

In this manner, the simulation method of the present invention allows logic simulation of a plurality of test patterns at the same time.

FIG. 4 shows a 0°1-stuck-at fault defined at the element input of FIG. fl r f2 are each element 20
rf5 is the second input terminal of the element 20 (1 indicates a stuck-at fault after two constants).Similarly, +f4+f5 is ,
〇 indicates a stuck-at fault and 1 indicates a stuck-at fault defined at one input terminal of the element 60, respectively; rf6 indicates the other input terminal of the element 30 (
One defined 1 - indicates a stuck-at fault. Furthermore, +f8 is element 4
〇- indicates a stuck-at fault defined on one input terminal of 0 +
f7 + f9 are the other input terminals of the element 40 (0-stuck-at fault after two constants), respectively.

1 - Indicates a stuck-at fault.

FIG. 5 shows an example in which the fault fi+f2 r f5 at the input of the element 20 of rank 2 is simulated in contrast to the test pattern (2) of FIG.

1) Test pattern (2) set to the rank 1 input terminal is transmitted to the calculation mechanisms of the rank 2 and 3 elements.

II) Element 20 of rank 2 is used for positive logic simulation, and elements 21, 22 and 23 have 〇-
Stuck-at fault @f+, 1-stuck-at fault f2 and 1-stuck-at fault f3
is set.

When a fault is set, rank 2 elements 20 to 23 are simulated simultaneously. Since the only element that differs from the positive logic simulation value of element 20 is element 21, this 0-stuck-at fault f1 is transmitted to elements 31 and 41 of the next rank (rank 3). During propagation, the corresponding model number and fault number (in this example, the first model and the stuck-at fault f1) are transmitted.

iv) Next, in rank 3, the positive logic simulation and the simulation of the propagated O-stuck-at fault f1 are executed simultaneously, and the results are compared.

As a result, only the output of the element 31 differs from the positive logic value, so the stuck-at fault f1 propagates to the primary output terminal 50 and is detected as a fault.

FIG. 6 (Secondly, similarly, for the test pattern ■ in FIG. 4, the failure f4 r at the input of the element 60 of rank 3
An example is shown to simulate f5 t f6. In this example, a 1-stuck-at fault f6 is detected.

As described above, according to the present invention, a plurality of faults (generally, six faults in one example of (k-1) faults) can be simulated simultaneously.

In this example, an example is shown in which the application is applied to a small-scale logic circuit, but in the case of a large-scale logic circuit (2), one circuit is divided into n submodels, and the elements in the submodels of the same rank are If both are simulated at the same time, the processing speed will be even faster.

Such allocation by division is effective when the arithmetic mechanism is implemented in hardware.

〔Effect of the invention〕

As explained above, the present invention has k (k≧2) arithmetic mechanisms, so that it is possible to simultaneously simulate fi test patterns during logic simulation.
, During fault simulation, there is an effect that (k-1) faults can be simulated simultaneously.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a simulation method according to the present invention; FIG. 2 is a circuit diagram showing a logic circuit used to explain the simulation method of the present invention;
The figure shows the calculation process of multiple models for multiple test patterns using the circuit in Figure 1, and Figure 4 shows the calculation process of multiple models for multiple test patterns using the circuit in Figure 1.
FIG. 5 is a diagram showing failures defined at element inputs of the logic circuit shown in the figure, using the circuit of FIG. 4. FIG. 6 is a diagram showing an example of simulating the fault f1 + f2 + f3 at the input of the element of rank 2 for the test pattern (■), and the faults f4 and f5 + f6 at the input of the simulator. 10~13...Primary input, 20~23°30
~33.40~43...Element, 50.51...Primary output terminal, 60~67...Signal line between elements. Figure 2 - Rank Figure 6 - 1 Rank 0100 Loco 3 Figure

Claims (1)

[Claims] 1. Only data for one model is used as circuit elements and connection information between elements, and a maximum of k simulations are executed simultaneously by a calculation mechanism of k (k≧2) elements. , a logic circuit simulation method in which logic is propagated using k corresponding model numbers and logic values, and only elements in which an event occurs are subject to simulation. 2. The logic circuit simulation method according to claim 1, wherein a model to be modeled including connection information is divided into n sub-models, and the n sub-models are executed simultaneously. 3. The method of simulating a logic circuit according to claim 1 or 2, wherein the elements are ranked from primary input to primary output or from register to register, and the simulation is performed in units of ranks.