JPH01112840A - Communication control equipment - Google Patents

Abstract

PURPOSE:To improve operability, and at the same time, to prevent the decrease of reliability due to mis-setting, in a communication control device to be provided in a terminal equipment to transmit and receive data to and from a common transmission line by providing a means to calculate automatically a belonging group number from a set self address. CONSTITUTION:Switches 25, 26, 27 set up the lowest order bits b0, b1, b2 of the self address. When a received packet is a multiple address packet, an adder 29 adds '4' or '0' to the output contents from a register 28 according as the contents of b0 is '1' or '0' respectively, and outputs them. Next, the adder 30 adds '2' or '0' to the output contents from the adder 29 according as the contents of b1 is '1' or '0' respectively, and outputs them. Next, the adder 31 adds '1' or '0' to the output contents from the adder 30 according as the contents of b2 is '1' or '0' respectively, and outputs them as R. R is the group number to be required. An AND circuit 34 takes the logical product of R-th power of 2 and a transmission destination address 33 of the received packet, and if the result S is other than '0', it decides that the packet is addressed to its own group, and transfers the packet to a host terminal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention considers a network system in which a plurality of terminal devices (hereinafter also simply referred to as terminals) are connected to a common transmission path and communicate with each other. It relates to a communication control device installed in the terminal, and more specifically, broadcast communication in which the plurality of terminals are divided into several groups and a signal with the same content is sent to each terminal belonging to the same group at once. The present invention relates to a communication control device equipped with means for making it possible to receive such broadcast communication.

[Conventional technology]

BACKGROUND ART Home bus systems, which connect electrical devices in the home and operate and manage them, are attracting attention.

This home bus system is a system in which terminals such as electrical devices are connected to a common transmission path (bus), and the terminals are controlled and data is sent and received via the bus. In this home bus system, each terminal is connected to the bus via an interface unit (hereinafter abbreviated as IFU), and each data is transmitted in the form of a packet.

FIG. 9 is a block diagram showing such an IFU, and FIG.
The figure is a configuration diagram of a packet.

In FIG. 9, 1 is a home bus, 2 is a host device (terminal), 3 is a parallel/serial conversion circuit, 4 is a transmission control circuit, and 5
is N RZ (Non
Return to Zero) code or AMl
(Alternate Mark Inver
sion) code, a transceiver circuit is used to encode and decode these codes, 6 is a reception control circuit, 7 is a serial/parallel converter circuit, 8 is a buffer circuit for storing received data, and 9 is assigned to the own terminal. 10 is a self-address determination circuit that determines whether a packet received from the home bus 1 is addressed to the self-address, and 11 is a group number to which the self-terminal belongs. The dip switch 12 for setting is a self-group determination circuit that determines whether a packet received from the home bus 1 is addressed to (broadcast communication of) the group to which the self-terminal belongs. Note that, from a functional perspective, the IFU can be said to include a communication control circuit for the host device (terminal) 12 to transmit and receive data to and from the home bus l.

In Figure 1O, 15 is a priority code, 16 is a source address, 17 is a destination address, 18 is a control code, 1
9 is the message length, 20 is the data, 2R is the frame check code, 22 is the response signal from the destination, and 2R and 2
The period 2 is a dummy bit period, and error detection is performed during this period.

The packet format is as described above.

Please refer to FIGS. 9 and 10. In the home bus system, there are two cases in determining which packets to receive and import into the host device 2 among the packets transmitted on the home bus l.

One is when the packet is an individual notification signal, and this is represented by setting bit position "6°" (priority code usually consists of 1 byte) of priority code 15 in the packet to 0. The self-destination determination circuit 10 connects the home bus 1 to the transceiver 5, the reception control circuit 6, and the serial
The destination address 17 of the packet received in the buffer 8 via the parallel converter circuit 7 is compared with the self address set in the deep switch 9, and only if the two match, this packet is completed at the own terminal. The host device 2 determines that it is a real object, transmits it to the host device 2, and imports it.

The other case is when the packet is a relay notification signal, and this is represented by setting bit position "6" of priority code 15 to 1. At this time, the self-group destination determination circuit 12 similarly identifies the self-group (a group consisting of a plurality of terminals including the self-terminal) set by the dip switch 11 in the destination address field 17 of the packet received in the buffer 8. Corresponding bit position (for example, bit 3 for group 3)
If 1 is set in , it is determined that the broadcast notification is addressed to the self-group, and the packet in buffer 8 is sent to host device 2.
Transmit and import to.

Here, we will explain how the self-address assigned to the own terminal and the self-group address (group number of the self-group) assigned to multiple terminals including the own terminal are defined in a dot-like relationship. put.

FIG. 11 is an explanatory diagram showing the format of the self address. As shown in the figure, the self-address is represented by a total of 8 bits, the lower 4 bits and the upper 4 bits, so the number of self-addresses that can be assigned to each terminal is 26 = 256. be.

FIG. 12 is an explanatory diagram of the relationship between the self address and the self group address. In other words, the upper 4 bits are displayed in hexadecimal (0 to
In addition to 9, 10 is A, 11 is B112, C113 is D,
14 is expressed as E and 15 as F) and arranged on a horizontal shelf, and the lower 4 bits are similarly expressed in hexadecimal and arranged in a vertical column, as shown in Figure 12, the lower 4 bits are
All self-addresses whose bits are expressed as O or 8 in hexadecimal notation belong to group 0, and all self-addresses whose lower 4 bits are expressed as 4 or C (12) in hexadecimal notation belong to group 1, and the following Similarly, the lower 4 bits are 16
All self-addresses expressed as 7 or F(15) in decimal notation are determined to belong to group 7.

The communication control method of this home bus system is described in the "Home Bus System Standard Use Study Report" February 1988 EI
It is detailed in the AJ/Radio Association Joint HBS Standards Committee publication. This committee belongs to the HBS Study Group of the Japan Electronics Industry Association, which is an organization that promotes standardization work for home bus systems.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the user sets the belonging group number determined by the user's own address. Therefore, self-address and Guruleaf.

This required a number correspondence table, which caused problems in terms of operability. Additionally, incorrect settings can cause malfunctions, resulting in lower reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication control device that eliminates the above-mentioned problems of the prior art, automatically calculates and sets a group number simply by setting a self-address, and enables correct reception of group broadcast packets. It's about doing.

[Means for solving problems]

The above object is achieved by providing means for automatically calculating the group number to which the device belongs based on the set self-address.

[Effect]

The calculation means automatically calculates its own group number based on the set bit data of its own address. Thereby, it is determined whether or not to receive a broadcast packet, so there is no need for the user to set a group number, and a decrease in reliability due to incorrect settings can also be avoided.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing essential parts of a first embodiment of the present invention. In the same figure, 25 is the lowest pin of the self-address setting switch) bo (see Figure 11), 26 is the same bit b3.27 is the same bit b2.28 is the register, 2
9° is an adder that adds 4 to the content from the register 28 and outputs it if the content of bit b0 of switch 25 is 1, and adds 0 to the content if bo is O, and 30 is an adder that outputs the result.
If the content of bit b1 of switch 27 is 1, 2 is added to the output content from adder 29, and if it is O, 0 is added and output. 32 is a shift register for calculating 2 to the R power (where R is the output of adder 31);
3 is the destination address of the received packet, and 34 is an AND circuit.

Next, the operation of the first embodiment will be explained with reference to the flowchart shown in FIG. First, set the self address using the dip switch as B(be, b,).

bt,...by) and the register 28 in Fig. 2 40)
Clear the contents (Figure 2, 41).

If bit 6 of the priority code of the received packet is 1, this is a broadcast packet, so if the content of bit b0 of the switch 25 is 1, the register 28
If the content of bt is 1, add 4 to the output content, and if it is 0, add O and output it (Fig. 2 42-43). 2 is added to the output content, and if it is 0, O is added and output (Figure 2 44.45).

Next, the adder 31 determines that the content of bit b2 of the switch 27 is 1.
If so, add 1 to the output content from the adder 30, and if it is 0, add O and output it as R (Figure 2 46.47).
The content R obtained by calculation in this way is the group number to be sought.

Next, the shift register 32 calculates 2 to the R power.

The AND circuit 34 takes the AND of this 2 to the R power and the destination address 33 of the received packet (see FIG. 2, 48.
49), if S is 0, it is determined that the packet is not addressed to the self-group (Fig. 2, 51), and if S is other than O, it is determined that the packet is addressed to the self-group.
FIG. 50), transfers the packet to the host terminal.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing the main parts of a second embodiment of the present invention. In the figure, 55 is a self-address setting section, 56 is a buffer, 57 is also a buffer, 58 is a shift register, 5
9 is also a shift register, and 60 is the destination address of the received packet.

Next, the operation of the second embodiment will be explained with reference to the flowchart of FIG. First, the set self-address is set as B (FIG. 4, 65), and the data with the bit position inverted is copied to the buffer 56 as a reverse hexadecimal (reverse hexadecimal 1 representation) (FIG. 4, 66).

Next, the data in the buffer 56 with the lower four bits and nodes set to O is copied to the buffer 57 (FIG. 4, 67).

Next, the data in the buffer 57 is shifted to A by the shift register 58 (41st ffi6B). The result of this calculation is G
becomes the desired group number.

Next, the shift register 59 calculates 2 to the G power (
Figure 4 69). The logical AND of this result H and the destination address 60 of the received packet is performed (70 in FIG. 4),
If the resulting I is O, it is determined that the packet is not addressed to the self-group. T2), if l is 0
If it is not, it is assumed that it is addressed to the self-group.Figure 4-7
1.73), forward the packet to the host.

Next, a third embodiment of the present invention will be described.

FIG. 5 is a block diagram showing the main parts of a third embodiment of the present invention. In the figure, 75 is a buffer register that stores self address B, 76 is an 8-bit shift register, and 77
78 is a remainder detection circuit, 78 is an 8-bit shift register, and 79 is a remainder detection circuit.
is a remainder detection circuit, 80 is an 8-bit shift register, 81
is a remainder detection circuit, 82 is a register, and 83 is a remainder detection circuit.If the content of the remainder detection circuit 77 is 1, the output content of the register 82 is 16.
An 8-bit shift register that multiplies and outputs the result; 84 is an 8-bit shift register that multiplies the output content of the shift register 83 by 4 and outputs the result when the content of the remainder detection circuit 79 is 1;
5 is an 8-bit shift register that doubles the output content of the shift register 84 and outputs it if the content of the remainder detection circuit 81 is 1; 86 is the destination address of the received packet;
7 is an AND circuit.

Next, the operation of the third embodiment will be explained with reference to the flowchart shown in FIG. First, copy the self-address B set by the dip switch to the buffer register 75 (Fig. 6, 90), and set the contents of the register 82 to 01 (
Figure 6 91). Next, the shift register 76 %s the contents of the buffer register 75 and calculates the remainder as a remainder detection circuit 77-
1 input (Figure 6, 92). If the content of the remainder detection circuit 77 is 1, the shift register 83 multiplies the content of the buffer register 82 by 16 and outputs it (Fig. 6, 93.94).
).

Next, the shift register 78 further increments the contents of the register 76 (reset as B) and inputs the remainder to the remainder detection circuit 79 (FIG. 6, 95).

If the content of the remainder detection circuit 79 is 1, the shift register 84 further multiplies the output content of the register 83 (hereinafter referred to as D) by 4 and outputs the result (FIG. 6, 96 and 97).

Next, the shift register 80 further %s the contents of the register 78 (this will be referred to as B again), and the remainder is sent to the remainder detection circuit 8.
1 (FIG. 6, 98). The shift register 85 is
If the content of the remainder detection circuit 81 is 1, the content of the register 84 (this will be renamed D) is further doubled and output (99.100 in FIG. 6).

Next, the AND circuit 87 performs the AND of the output contents of the register 85 (hereinafter referred to as D) and the destination address 86 (DA) of the received packet (see FIG. 6, 10).
1), if the resulting C is 0, it can be determined that the packet is not addressed to the self-group.
If is other than 0, it is determined that it is addressed to the self-group (
Figure 6 102, 104).

Next, a fourth embodiment of the present invention will be described.

FIG. 7 is a configuration diagram showing a main part of a fourth embodiment of the present invention. In the figure, 105 is a buffer for copying the own address B, and 106 is a ROM (Read) into which group numbers corresponding to each address are input as a table.
0nly Memory), 107 is ROM106
108 is a buffer for storing the destination address DA of the received packet, 109 is an 8-bit shift register, and 110 is a remainder detection circuit.

Next, the operation of the fourth embodiment will be explained with reference to the flowchart of FIG. 8. By inputting the contents of the self-address B from the buffer 105 to the ROM 106, the group number to which the self-address belongs is stored in the buffer 107.
(115, 116, 117 in Fig. 8). The shift register 109 shifts the contents DA of the destination address of the buffer 10B (L+1) times and outputs the shifted contents (119.120, 12R.122 in FIG. 8). If the remainder W is 0, the remainder detection circuit 110 determines that the packet is not addressed to the self-group (Fig. 8, 124);
If it is other than that, it is determined that it is addressed to the self-group (8th
Figure 125).

As described above, according to this embodiment, by simply setting the user's own address, the group number to which the user belongs can be automatically calculated based on it, and it can be determined whether or not to receive the broadcast packet. This eliminates the need for the user to set the group number, and also eliminates the reduction in reliability due to incorrect settings.

〔Effect of the invention〕

As described above, according to the present invention, by simply setting the user's own address, the group number to which the user belongs can be automatically calculated based on it, and it can be determined whether or not to receive broadcast packets. This has the effect of improving operability since the user does not need to set a group number. It also has the effect of eliminating a decrease in reliability due to incorrect settings.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of the first embodiment of the present invention, FIG. 2 is a flowchart showing the operation flow of the first embodiment, and FIG. 3 is a block diagram of the second embodiment of the present invention. A configuration diagram showing the main parts,
FIG. 4 is a slow chart showing the flow of the operation of the second embodiment, FIG. 5 is a configuration diagram showing the main parts of the third embodiment of the present invention, and FIG. 6 is a flow chart showing the operation of the third embodiment. FIG. 7 is a block diagram showing the main part of the fourth embodiment of the present invention. FIG. 8 is a flowchart showing the operation flow of the fourth embodiment. FIG. 9 is a flowchart showing the operation flow of the fourth embodiment of the present invention. A block diagram showing an example of the configuration of the ink face unit, FIG. 10 is an explanatory diagram showing the packet configuration (format), and FIG.
The figure is an explanatory diagram showing the format of self-address, No. 12.
The figure is an explanatory diagram of the relationship between self-addresses and self-group addresses. Explanation of symbols 25 to 27...Self address setting switch, 28...
・Registers, 29-31...Adder, 32...Shift register, 33...Transmission destination address section, 34...
・Logic product circuit, 109...shift register, 110・
...Remainder detection circuit agent Patent attorney Akira Namiki Futomi Figure 1 2R! 1 13m 1F4 Figure 15 Figure π6111 Neck 7 Figure B ROM 118 Figure

Claims (1)

[Claims] 1. In a communication control device provided in a terminal device that is connected to a common transmission path and sends and receives data to and from the common transmission path, a communication control device that sets a self-address assigned to the own terminal device; an address setting means; a destination address included in the packet signal for determining and capturing when the packet signal transmitted on the common transmission path is an individual report signal and a signal addressed to the terminal device; self-destination address determining means for comparing the self-destination address with the self-address set by the self-address setting means; and the packet signal transmitted on the common transmission path is a broadcast notification signal, and is composed of a plurality of terminal devices including the own terminal device. self-group address determination means for comparing a destination address included in the packet signal with a self-group address assigned to the self-group in order to determine and capture the signal when the signal is addressed to the self-group; A communication control device, further comprising: self-group address calculation means for receiving the self-address and calculating the self-group address to be assigned to the self-group. 2. In the communication control device according to claim 1, the self-group address calculation means sets the least significant bit of the given self-address to the square of 2, and the second bit from the lowest to the power of 2. A communication control device comprising means for calculating by weighting the third bit from the lowest to the 1st power and 2 to the 0th power, and calculating the sum thereof. 3. In the communication control device according to claim 1, the self-group address calculation means comprises a storage means for storing the self-address and the self-group address in association with each other in advance, and stores the self-address in the storage means. A communication control device that inputs and outputs a corresponding self-group address. 4. In the communication control device as set forth in claim 1, the self-destination address determining means is configured to determine whether the destination address included in the packet signal and the group number as the self-group address are R. A communication control device comprising means for calculating the logical product of the value of 2^R and the value of 2^R. 5. In the communication control device as set forth in claim 1, the self-group address determination means, where R is the group number as the self-group address,
A communication control device comprising means for making a determination based on a result obtained by shifting the destination address of the packet signal in the direction of the lower bits (R+1) times.