JPH01115145A - Resin sealed type integrated circuit - Google Patents
Resin sealed type integrated circuitInfo
- Publication number
- JPH01115145A JPH01115145A JP27456287A JP27456287A JPH01115145A JP H01115145 A JPH01115145 A JP H01115145A JP 27456287 A JP27456287 A JP 27456287A JP 27456287 A JP27456287 A JP 27456287A JP H01115145 A JPH01115145 A JP H01115145A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- package
- metal
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマイクロコンピュータやCPU等の高速動作モ
ノリシックICに関し、特にその樹脂パッケージに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high-speed operation monolithic ICs such as microcomputers and CPUs, and particularly to resin packages thereof.
従来、8ビツト、16ビツト、32ビツトのCPU や
エチツプマイコンのパッケージは、主に第3図および第
4図に示すような樹脂封止形のものが使用されている。Conventionally, packages for 8-bit, 16-bit, and 32-bit CPUs and chip microcomputers have mainly been of the resin-sealed type as shown in FIGS. 3 and 4.
第3図は樹脂封止形集積回路をパッケージの一部を破断
して示す斜視図、第4図はその側面図である。これらの
図において、1は集積回路チップ、2は金属リード、3
は前記集積回路チップ10表面電極(図示せず)と金属
リード2とを接続するための金細線、4はこれら集積回
路チップ1.金属リード2.金細線3を封止すると共に
パッケージ5を形成するエポキシ樹脂である。FIG. 3 is a perspective view showing a resin-sealed integrated circuit with a part of the package cut away, and FIG. 4 is a side view thereof. In these figures, 1 is an integrated circuit chip, 2 is a metal lead, and 3 is an integrated circuit chip.
Reference numeral 4 indicates a thin gold wire for connecting the surface electrode (not shown) of the integrated circuit chip 10 and the metal lead 2, and 4 indicates the integrated circuit chip 1. Metal lead 2. This is an epoxy resin that seals the thin gold wire 3 and forms the package 5.
このように構成されたCPU等の集積回路は、その動作
周波数が命令語長の拡大と処理機能の高度化に伴い10
MHz〜20MHzという高速で動作するものが実用化
されている。The operating frequency of integrated circuits such as CPUs configured in this way has increased to 10
Devices that operate at high speeds of MHz to 20 MHz have been put into practical use.
しかるに、集積回路の動作の高速化に伴い集積回路チッ
プの表面から高周波が発生し、樹脂パッケージは電磁波
に対しては遮蔽能力がないため、周辺機器に電波障害を
引き起こすという問題があった。However, as integrated circuits operate at higher speeds, high frequencies are generated from the surface of integrated circuit chips, and resin packages do not have the ability to shield electromagnetic waves, causing electromagnetic interference in peripheral devices.
本発明に係る樹脂封止形集積回路は、集積回路パンケー
ジの表面に金属膜を形成し、この金属膜を接地したもの
である。The resin-sealed integrated circuit according to the present invention has a metal film formed on the surface of an integrated circuit pancake, and this metal film is grounded.
集積回路チップが発する電磁波は金属膜によって遮蔽さ
れる。The electromagnetic waves emitted by the integrated circuit chip are shielded by the metal film.
以下、その構成等を図に示す実施例により詳細に説明す
る。第1図は本発明に係る金属薄膜が形成された樹脂封
止形集積回路をパッケージの一部を破断して示す斜視図
である。同図において前記従来例で説明したものと同一
もしくは同等部材については同一符号を付し、詳細な説
明は省略する。Hereinafter, its configuration and the like will be explained in detail with reference to embodiments shown in the drawings. FIG. 1 is a perspective view showing a resin-sealed integrated circuit on which a metal thin film according to the present invention is formed, with a part of the package cut away. In the figure, the same or equivalent members as those explained in the conventional example are given the same reference numerals, and detailed explanations will be omitted.
同図において、11は電磁波を遮蔽するための金属薄膜
で、この金属薄膜11は、パッケージ5における集積回
路チップ1の表面1aと平行な面5a上にスパッタリン
グあるbは無電解メツキによって形成されている。12
は前記金属薄膜11とアース用リード13とを接続する
ための金R簿膜で、前記金属薄膜11と同様にスパッタ
リングあるいは無電解メツキによってパッケージ5の側
面に形成されている。すなわち、パッケージ50面5畠
上に金属薄膜11を形成するには、樹脂封止後に金属リ
ード2およびパッケージ5の側面を治具(図示せず)で
覆い、スパッタリングあるいは無電解メツキを施すこと
によって行なわれる。In the figure, 11 is a metal thin film for shielding electromagnetic waves, and this metal thin film 11 is formed by sputtering on a surface 5a parallel to the surface 1a of the integrated circuit chip 1 in the package 5, and b is formed by electroless plating. There is. 12
is a gold R-type film for connecting the metal thin film 11 and the grounding lead 13, and is formed on the side surface of the package 5 by sputtering or electroless plating like the metal thin film 11. That is, in order to form the metal thin film 11 on the package 50 surface 5, the metal leads 2 and the side surfaces of the package 5 are covered with a jig (not shown) after resin sealing, and sputtering or electroless plating is performed. It is done.
したがって、集積回路チップ1の表面1aから発せられ
る数十MHz〜数百MHzの高周波の電気力線の向きは
、集積回路チップ1の表面1aに対して直交する方向で
あるから、金属薄膜11を集積回路チップ10表面1m
と平行に形成し、かつアース用リードを介して接地させ
ることによって、集積回路チップ1から発せられる高周
波は完全に遮蔽されることになる。Therefore, since the direction of the high frequency electric lines of force of several tens of MHz to several hundreds of MHz emitted from the surface 1a of the integrated circuit chip 1 is perpendicular to the surface 1a of the integrated circuit chip 1, the metal thin film 11 is Integrated circuit chip 10 surface 1m
By forming the integrated circuit chip 1 in parallel with the integrated circuit chip 1 and grounding it through a grounding lead, the high frequency waves emitted from the integrated circuit chip 1 can be completely shielded.
また、本実施例では金属薄膜11は金属薄膜12および
アース用リード13を介して接地されているが、この金
属薄膜12およびアース用リード13を用いずに、この
集積回路が実装される基板(図示せず)のアースに電気
的に接続すれば同等の効果が得られる。さらに1金属薄
膜11をパッケージ5の裏面にも形成し、接地させるこ
とによって遮蔽効果を向上させることができる。Further, in this embodiment, the metal thin film 11 is grounded via the metal thin film 12 and the grounding lead 13, but the substrate on which this integrated circuit is mounted ( The same effect can be obtained by electrically connecting it to the ground (not shown). Furthermore, the shielding effect can be improved by forming the metal thin film 11 on the back surface of the package 5 and grounding it.
なお、本実施例では金属リード2が集積回路の四方に配
置されたデュアル・インラインタイプの集積回路にりい
て説明したが、本発明に係る樹脂封止形集積回路は、こ
のような限定にとられれることなく、例えば第2図に示
すような集積回路にも応用することができる。第2図(
&) 、 (b) 、 (C)はシングル・インライン
タイプの樹脂封止形集積回路を示す正面図、側面図およ
び底面図でおる。同図において第1図に示す部材と同一
もしくは同等部材については同一符号を付し、ここにお
いて詳細な説明は省略する。Although this embodiment has been described with reference to a dual in-line type integrated circuit in which metal leads 2 are arranged on all sides of the integrated circuit, the resin-sealed integrated circuit according to the present invention is not subject to such limitations. For example, it can be applied to an integrated circuit as shown in FIG. 2 without being limited. Figure 2 (
&), (b), and (C) are a front view, a side view, and a bottom view showing a single in-line type resin-sealed integrated circuit. In this figure, members that are the same as or equivalent to those shown in FIG. 1 are denoted by the same reference numerals, and detailed explanations are omitted here.
また、集積回路の周辺を覆うように金属キャップを被冠
させ、この金属キャップを接地させる構造のパッケージ
は最も電磁遮蔽効果が大きいが、パッケージの製造コス
トが高くなり、かつ組立性も悪い。これに比べ本発明に
係る樹脂封止形集積回路は、樹脂封止パッケージに直接
金属薄膜を形成したため、製造コストを低く抑えること
ができると共に、自動化がはかれ容易に量産することが
できる。Furthermore, a package with a structure in which a metal cap is placed around the integrated circuit and the metal cap is grounded has the highest electromagnetic shielding effect, but the manufacturing cost of the package is high and assembly efficiency is poor. In contrast, in the resin-sealed integrated circuit according to the present invention, since the metal thin film is directly formed on the resin-sealed package, the manufacturing cost can be kept low, and it can be automated and easily mass-produced.
以上説明したように本発明によれば集積回路パッケージ
の表面に金属膜を形成し、この金属膜を接地したため、
集積回路チップが発する電磁波は金属膜によって遮蔽さ
れるから、周辺機器が電波障害を起こすようなことはな
い。As explained above, according to the present invention, a metal film is formed on the surface of an integrated circuit package and this metal film is grounded.
The electromagnetic waves emitted by the integrated circuit chip are shielded by the metal film, so there is no interference with peripheral devices.
第1図は本発明に係る樹脂封止形集積回路をパッケージ
の一部を破断して示す斜視図、第2図は他の実施例を示
す図、第3図は従来の樹脂封止形集積回路をバクケージ
の一部を破断して示す斜視図、第4図はその側面図でろ
る。
50.拳、パッケージ、110.11.金属薄膜。Fig. 1 is a perspective view showing a resin-sealed integrated circuit according to the present invention with a part of the package cut away, Fig. 2 is a diagram showing another embodiment, and Fig. 3 is a conventional resin-sealed integrated circuit. FIG. 4 is a perspective view showing the circuit with a part of the back cage cut away, and FIG. 4 is a side view thereof. 50. fist, package, 110.11. Metal thin film.
Claims (1)
属膜を接地したことを特徴とする樹脂封止形集積回路。A resin-sealed integrated circuit characterized by forming a metal film on the surface of an integrated circuit package and grounding the metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27456287A JPH01115145A (en) | 1987-10-28 | 1987-10-28 | Resin sealed type integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27456287A JPH01115145A (en) | 1987-10-28 | 1987-10-28 | Resin sealed type integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01115145A true JPH01115145A (en) | 1989-05-08 |
Family
ID=17543460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27456287A Pending JPH01115145A (en) | 1987-10-28 | 1987-10-28 | Resin sealed type integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01115145A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990001668A (en) * | 1997-06-17 | 1999-01-15 | 윤종용 | Electromagnetic Shielding Semiconductor Package |
| US5917241A (en) * | 1996-05-23 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | High frequency semiconductor device having source, drain, and gate leads |
| JP2009290217A (en) * | 2008-05-30 | 2009-12-10 | Yoon Jum-Chae | Semiconductor package having electromagnetic interference-shielding function, method of manufacturing the same, and jig |
| JP2017168704A (en) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and semiconductor device |
-
1987
- 1987-10-28 JP JP27456287A patent/JPH01115145A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917241A (en) * | 1996-05-23 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | High frequency semiconductor device having source, drain, and gate leads |
| KR19990001668A (en) * | 1997-06-17 | 1999-01-15 | 윤종용 | Electromagnetic Shielding Semiconductor Package |
| JP2009290217A (en) * | 2008-05-30 | 2009-12-10 | Yoon Jum-Chae | Semiconductor package having electromagnetic interference-shielding function, method of manufacturing the same, and jig |
| JP2017168704A (en) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN107204312A (en) * | 2016-03-17 | 2017-09-26 | 东芝存储器株式会社 | The manufacture method and semiconductor device of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100473261B1 (en) | Semiconductor device | |
| EP1012968A1 (en) | Shielded surface acoustical wave package | |
| JP2000223653A (en) | Semiconductor device having chip-on-chip structure and semiconductor chip used therefor | |
| JP2600366B2 (en) | Semiconductor chip mounting method | |
| US5349233A (en) | Lead frame and semiconductor module using the same having first and second islands and three distinct pluralities of leads and semiconductor module using the lead frame | |
| JPS5992556A (en) | Semiconductor device | |
| CN210489609U (en) | Integrated circuit package | |
| JPH01115145A (en) | Resin sealed type integrated circuit | |
| US12575447B2 (en) | QFN packaging structure and QFN packaging method | |
| JPH01138739A (en) | Integrated circuit package | |
| JPH06326218A (en) | Semiconductor device | |
| JP6494723B2 (en) | Semiconductor package | |
| JP2809212B2 (en) | Electronic device package | |
| JPH01241848A (en) | Ic device | |
| JPS5891646A (en) | Semiconductor device | |
| JPS60263451A (en) | Integrated circuit package | |
| JPH10284633A (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| JPH065657A (en) | Semiconductor device | |
| JPH10242362A (en) | Lead frame, semiconductor device, and method of manufacturing semiconductor device | |
| JPH03263360A (en) | Semiconductor device | |
| JPH1187410A (en) | Semiconductor device | |
| JP2514430Y2 (en) | Hybrid IC | |
| JPS60254755A (en) | Package for mounting semiconductor | |
| JPS63288034A (en) | Semiconductor device | |
| JPH06169047A (en) | Semiconductor device |