JPH01116439U - - Google Patents

Info

Publication number
JPH01116439U
JPH01116439U JP1988011857U JP1185788U JPH01116439U JP H01116439 U JPH01116439 U JP H01116439U JP 1988011857 U JP1988011857 U JP 1988011857U JP 1185788 U JP1185788 U JP 1185788U JP H01116439 U JPH01116439 U JP H01116439U
Authority
JP
Japan
Prior art keywords
semiconductor package
determination index
deviation determination
pattern deviation
exposed substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988011857U
Other languages
English (en)
Other versions
JPH075635Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988011857U priority Critical patent/JPH075635Y2/ja
Publication of JPH01116439U publication Critical patent/JPH01116439U/ja
Application granted granted Critical
Publication of JPH075635Y2 publication Critical patent/JPH075635Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires

Landscapes

  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例に係るＰＧＡタイプ
の半導体パツケージにワイヤボンデイングをする
前の平面図、第２図はＰＧＡタイプの半導体パツ
ケージにワイヤボンデイングをした後の断面図、
第３図はパターンずれ判定インデツクスの形状を
示す説明図、第４図ａ，ｂは上段及び下段のそれ
ぞれに露出したパターンの重なり具合を示す説明
図である。 図において、１は半導体パツケージ、２はパタ
ーン、２ａは露出したパターン、３は基板、３ａ
は上段の層の基板、３ｂは下段の層の基板、５は
パターンずれ判定インデツクスをそれぞれ示す。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 導体パターン２を印刷した基板３同士を多
    段に積層した上段と下段の対応する位置の各露出
    基板上に、パターンずれ判定インデツクス５を設
    けたことを特徴とする半導体パツケージ。 (2) 上記パターンずれ判定インデツクス５は、
    上段と下段の対応する位置の各露出基板上の少な
    くとも対角線上のコーナーに設けられていること
    を特徴とする実用新案登録請求の範囲第１項記載
    の半導体パツケージ。 (3) 上記パターンずれ判定インデツクス５は、
    上段及び下段の一方が凹部形状で、他方が該凹部
    の溝幅間に位置する凸部形状に形成されているこ
    とを特徴とする実用新案登録請求の範囲第１項ま
    たは第２項記載の半導体パツケージ。
JP1988011857U 1988-01-29 1988-01-29 半導体パッケージ Expired - Lifetime JPH075635Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988011857U JPH075635Y2 (ja) 1988-01-29 1988-01-29 半導体パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988011857U JPH075635Y2 (ja) 1988-01-29 1988-01-29 半導体パッケージ

Publications (2)

Publication Number Publication Date
JPH01116439U true JPH01116439U (ja) 1989-08-07
JPH075635Y2 JPH075635Y2 (ja) 1995-02-08

Family

ID=31220777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988011857U Expired - Lifetime JPH075635Y2 (ja) 1988-01-29 1988-01-29 半導体パッケージ

Country Status (1)

Country Link
JP (1) JPH075635Y2 (ja)

Also Published As

Publication number Publication date
JPH075635Y2 (ja) 1995-02-08

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