JPH0353853U - - Google Patents

Info

Publication number
JPH0353853U
JPH0353853U JP1989114513U JP11451389U JPH0353853U JP H0353853 U JPH0353853 U JP H0353853U JP 1989114513 U JP1989114513 U JP 1989114513U JP 11451389 U JP11451389 U JP 11451389U JP H0353853 U JPH0353853 U JP H0353853U
Authority
JP
Japan
Prior art keywords
recess
substrate
view
hybrid
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989114513U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989114513U priority Critical patent/JPH0353853U/ja
Publication of JPH0353853U publication Critical patent/JPH0353853U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は、本考案の実施例の断面図であり、第
２図は、くぼみを設けた面の平面図である。第３
図、第４図は実施例２のものであり、それぞれ断
面図、くぼみを設けた面の平面図である。第５図
は従来のハイブリツドＩＣの断面図である。 １……厚膜印刷基板、１′……従来の厚膜印刷
基板、２……ベアチツプ、３……ボンデイングワ
イヤ、４……プリコート樹脂、５……デイスクリ
ート部品。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板上の少なくとも一平面上にくぼみを設け、
    そのくぼみに半導体チツプを搭載し基板面を平ら
    になるように樹脂で封止することを特徴とするハ
    イブリツドＩＣ。
JP1989114513U 1989-09-29 1989-09-29 Pending JPH0353853U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989114513U JPH0353853U (ja) 1989-09-29 1989-09-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989114513U JPH0353853U (ja) 1989-09-29 1989-09-29

Publications (1)

Publication Number Publication Date
JPH0353853U true JPH0353853U (ja) 1991-05-24

Family

ID=31662877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989114513U Pending JPH0353853U (ja) 1989-09-29 1989-09-29

Country Status (1)

Country Link
JP (1) JPH0353853U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06334113A (ja) * 1993-05-21 1994-12-02 Sony Corp マルチチップモジュール
JP2001164619A (ja) * 1999-12-07 2001-06-19 Nihon Hels Industry Corp 蛇口等用抗菌キャップ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06334113A (ja) * 1993-05-21 1994-12-02 Sony Corp マルチチップモジュール
JP2001164619A (ja) * 1999-12-07 2001-06-19 Nihon Hels Industry Corp 蛇口等用抗菌キャップ

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