JPH01117355A - solid state imaging device - Google Patents

Abstract

PURPOSE:To contrive the improvement of the S/N and the resolution of solid-state image sensing device by a method wherein a fixed potential pattern is arranged between signal readout wirings and fixed potential patterns are each arranged between photoelectric conversion elements and externally attached parallel capacitor parts, both of which are respectively connected to the different signal readout wirings. CONSTITUTION:A fixed potential pattern 141 is arranged between signal readout wirings 114 and 124. Moreover, fixed potential patterns 142 are each arranged between a photoelectric conversion element 111 and an externally attached parallel capacitor part 112, which are connected to the wiring 114, and between a photoelectric conversion element 121 and an externally attached parallel capacitor part 122, which are connected to the wiring 124. Those fixed potential patterns stop the capacitance coupling between the signal readout wirings, between the photoelectric conversion elements and between the externally attached parallel capacitor parts. Thereby, the coupling capacitance 341 between the signal readout wirings; which is generated by a fact that the signal readout wirings run in parallel to each other and a fact that the photoelectric conversion elements and the externally attached parallel capacitor parts, both of which are respectively connected to the different signal readout wirings, are adjacent to each other; can be significantly reduced and a reduction in the crosstalk between the signal readout wirings can be contrived. Moreover, the improvement of the S/N and the resolution of a solid-state image sensing device can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for arranging elements and patterns of a -dimensional solid-state imager.

[Conventional technology]

FIG. 3 shows an example of a circuit using two signal readout wirings. In the figure, signal readout wiring,
The photoelectric conversion elements 313 and 323 connected to the photoelectric conversion elements 314 and 324 are simultaneously selected by the analog switches 313 and 323 in response to a signal from the scanning circuit 331, and signal charges are read out to the respective signal readout wirings.

・Using multiple signal readout wires in this format allows for a longer signal readout time from the selected photoelectric conversion element than when using only one signal readout wire, so the signal charge is reduced. The readout efficiency can be improved, the operating speed of the scanning circuit and signal succession circuit can be reduced, so noise generated in each part can be reduced, and the number of photoelectric conversion elements connected on the same signal readout wiring can be reduced. Therefore, by improving the selectivity for each photoelectric conversion element, the S/N ratio can be significantly improved, which is useful.

FIG. 2 is a pattern diagram showing the arrangement of photoelectric conversion elements, analog switches, signal readout lines, etc. of a solid-state imaging device using two conventional signal readout lines.

In the figure, 211 and 221 are photoelectric conversion elements, 212 and 2
22 is light [electricity generated in the conversion section (11r is '154i')
A parallel capacitor externally attached to the photoelectric conversion element to
13 and 223 are analog switches for selecting each photoelectric conversion element. The photoelectric conversion element 211 is connected to the signal readout wiring 214, and the photoelectric conversion element 221 is connected to the signal readout wiring 2.
In this way, the photoelectric conversion elements connected to the signal readout wiring 214 and the photoelectric conversion elements connected to the signal readout wiring 224 are arranged alternately.

Since the scanning circuit section and the analog switch control wiring 232 are the main sources of noise, it is very disadvantageous in terms of S/N to have the signal readout wiring adjacent to these and recross-under. For this reason, it is not possible to distribute and arrange the signal readout wiring on both sides of the photoelectric conversion element, and the signal readout wiring is placed on the opposite side of the photoelectric conversion element from the scanning circuit section and analog switch control wiring. .

[Problems to be Solved by the Invention] When the elements and wiring are arranged in the pattern shown in FIG.
Due to the existence of the photoelectric conversion elements and parallel capacitances connected to different signal readout wirings and the cross-under section 242 between the adjacent signal readout wirings, the signal readout wiring as shown in 341 in FIG. 3 actually exists. There will be a coupling capacitance between the two.

On the other hand, the photocharges accumulated in each photoelectric conversion element and external parallel capacitor are read out in a pulse to the signal readout wiring when that photoconversion element is selected, so this readout signal has quite high frequency components. It turns out. For this reason, crosstalk occurs between each signal readout wiring via the coupling capacitance 341 between the signal readout wirings, and the selection ratio between simultaneously selected photoelectric conversion elements decreases, resulting in a reduction in S/N and A problem arises in that the resolution decreases. This problem greatly reduces the advantages of using multiple signal readout wirings.

The present invention is intended to solve these problems, and its purpose is to improve the S/N and resolution of solid-state imaging devices by reducing the coupling capacitance between signal readout wirings. be.

[Means for solving problems]

The solid-state imaging device of the present invention has the following advantages: (1) A fixed potential pattern is arranged between each signal readout wiring;2. A feature is that a fixed potential pattern is arranged between photoelectric conversion elements connected to different signal readout wirings.

〔Example〕

FIG. 1(a) is a pattern diagram showing the arrangement of photoelectric conversion elements, analog switches, signal readout wiring, etc. of a solid-state imaging device according to an embodiment of the present invention, and shows a case where there are two signal readout wirings. FIGS. 1(b) and (C) are cross-sectional views taken at lines B and C in FIG. 1(a). 11 in the same figure
1 and 112 are photoelectric conversion elements consisting of a lower electrode made of a transparent conductive layer 103, an upper electrode made of a photoconductive layer 102 and a metal wiring layer 107, and are of a type that allows light to enter from the insulating transparent substrate 101 side. 112 and 122 are parallel capacitors externally attached to a photoelectric conversion element consisting of a lower electrode 1°8, an interlayer insulating film 104, and an upper electrode formed by a metal wiring layer 107, and 113 and 123 are analog switches made of thin film transistors.

A pattern 141 with a fixed potential is arranged between the signal readout wiring 114 and 124, and the photoelectric conversion element 111 and external parallel capacitor 112 connected to the signal readout wiring 114 and the photoelectric conversion element 141 connected to the signal readout wiring 124 are arranged. Element 12
A fixed potential pattern 142 is arranged between the capacitor 1 and the external capacitor 122. These fixed potential patterns prevent capacitive coupling between each signal readout line, the photoelectric conversion element, and the external parallel capacitor, so each signal readout line runs in parallel and is connected to a different signal readout line. Coupling capacitance 341 between signal readout wiring occurs due to adjacent parallel capacitance parts of photoelectric conversion elements and external devices
can be significantly reduced, and crosstalk between signal readout wirings can be reduced. Further, the fixed potential patterns 141 and 142 can be formed using the metal wiring layer 107, and can be applied without changing the manufacturing process from the conventional case. On the other hand, the presence of these fixed potential patterns increases the capacitances 1315 and 325 of the signal readout wiring to ground;
These capacitances and amounts work to reduce the impedance of the signal readout wiring during signal reading, and therefore work to reduce crosstalk between the signal readout wirings.

FIG. 4(a) is a pattern diagram showing another example of the solid-state imaging device according to the embodiment of the present invention, and FIG. 4(b) and (c)
) is a sectional view taken along lines B and C in FIG. 1(a). In the figure, reference numeral 441 indicates a fixed potential pattern provided in the interlayer insulating film 404. In this example, a pattern 441 with a fixed potential is formed by providing a conductive layer in the glabellar insulating film 404. Although the manufacturing process becomes somewhat complicated by adopting such a structure, the signal interconnections 414 and 424
Also in the cross-under portion, a fixed potential pattern can be arranged between each signal readout wiring. Therefore, the coupling capacitance between the signal readout wirings that occurs at the cross-under portion between each signal readout wiring can also be reduced.
Crosstalk between signal readout wirings in layers can be reduced.

The case where there are two signal readout wirings has been explained above, but
Needless to say, the same effect can be obtained even when there are three or more signal readout wirings.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the coupling capacitance between signal readout wirings in a solid-state imaging device using a plurality of signal readout wirings, and the S/
N and resolution can be improved.

[Brief explanation of the drawing]

FIG. 1(a) is a pattern diagram of a solid-state imaging device according to an embodiment of the present invention, and FIG. 1(b) and FIG. 1(c) are cross sections taken along lines B and C in FIG. 1(a). It is a diagram. FIG. 2 is a pattern diagram of a conventional solid-state imaging device. FIG. 3 is a circuit diagram when two signal readout wirings are used. FIG. 4(a) is a pattern diagram of another example of the solid-state imaging device according to the embodiment of the present invention, and FIG. 4(b) and FIG. 4(c) show the lines in FIG. 1(a). FIG. 101.401 ... Insulating transparent substrate 102.40
2...Photoconductive layer 103.403...Transparent conductive layer 105.405...Layer 106.406 which becomes the channel, source and drain portion of the thin film transistor...Gate wiring layer 107, 407 of the thin film transistor... Metal wiring layer 108.408... External parallel capacitance lower electrode (1
Same material as 06,406 f) 111.121, 211, 212, 411, 421...
・Photoelectric conversion elements 112, 122, 212, 222, 412, 422...
・External parallel capacitance section 113, 213, 223, 413, 423 for the photoelectric conversion element...
・Analog switch 114.124, 214, 224, 414, 424...
-Signal readout wiring 331 -...Scanning circuit 132, 232, 332, 432...Analog switch control wiring 141, 142, 441, 442...Fixed potential pattern 341...Signal readout Inter-wiring coupling capacitance 242
゛...Cross under section between signal readout wiring Applicant: Seiko Epson Corporation (α),) t4 N 4 ISUa Hime=-LaL: Mine!/
赫t (it) Figure 4 <C>

Claims (1)

[Claims] In a one-dimensional solid-state imaging device that has a plurality of signal readout wirings and simultaneously selects and reads out signals from a plurality of photoelectric conversion elements, a fixed potential pattern is defined between each signal readout wiring. A solid-state imaging device characterized in that a fixed potential pattern is arranged between photoelectric conversion elements connected to different signal readout wirings.