JPH01117405A - Operational amplifier - Google Patents

Abstract

PURPOSE:To attain optimization of power consumption by using a transistor(TR) array where gates of each MOS TR are connected in parallel via an analog switch. CONSTITUTION:N-channel MOS TR pairs M1, M2, P-channel MOS TR pairs M3, M4 being loads and sources of the N-channel MOS TR pairs M1, M2 are connected in common and they are connected to drains of N-channel MOS TRs M11-M1n. The sources of the N-channel MOS TRs M11-M1n are connected to ground in common. Drains of the N-channel MOS TRs M31-M3n are connected in common, gates of the N-channel MOS TRs M21-M2n are connected respectively to gates of the N-channel MOS TRs M11-M1n are connected respectively and connected to an output terminal O1 of analog switches B1-Bn consisting of switches S1, S2 and an inverter G1 and having input terminals I1, I2, an output terminal O1 and a control terminal C1. Thus, the power consumption is optimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an operational amplifier, and particularly to an operational amplifier configured with complementary MOS transistors (hereinafter referred to as CMO8).

[Conventional technology]

In recent years, the number of single-chip integrated circuits (hereinafter referred to as LSIs) that incorporate digital and analog circuits has been increasing. Especially in the analog field, Sui.

capacitor filter (hereinafter referred to as SCF), A/
Operational amplifiers using 0MO8, which are easy to configure as D converters, have become mainstream. Furthermore, there are many demands for lower voltage and lower power consumption, and a wide variety of LSIs with CMO8 configurations are now available. Among them, 0M
In the analog field of O8, operational amplifiers are important circuits.

Conventionally, the operational amplifiers in this building had circuit configurations as shown in FIGS. 4 and 5.

Figure 4 shows the first conventional example, Nch MOS)
.

Transistors Ml, M2. MIO and Pch MOS transistor M3. A differential amplification stage intertwined with M4 and Nc
h MOS) An output amplification stage consisting of a transistor M20 and a Pch MOS transistor M30, and an Nch MOS
) transistor M5. A bias stage consisting of a PchMOS transistor M6 and a PchMOS transistor M7, and a capacitor C for phase compensation.
It is composed of c.

A second conventional example is shown in FIG. The second conventional example has the same configuration as the first conventional example regarding the differential amplification stage and bias stage, but the output amplification stage is Nch MOS.
) Transistor M50 and PchMOS transistor M
between the differential amplification stage and the output amplification stage.
MOS) An output drive stage consisting of transistors M20 and M2O is included.

In addition, phase compensation is performed using Cc and Nch MOS) transistor M70 and Pch MOS) transistor M80.
It is made up of.

In the first conventional example, in order to obtain desired frequency characteristics with a low voltage power supply, a certain amount of current must flow through the differential amplification stage and the output amplification stage. The transistors that can control the current are MIO and M2O, and once the voltage of the bias stage is determined, the magnitude of the current is determined by MIO and M2O.
It is determined by the gate length of 2O and the gate width W. here,
The frequency characteristics are shown in FIG. 6, assuming that the low voltage power supply is VDD = 3.0 V. The solid line is VDD=3. The characteristics of OV are shown. The broken line indicates VDD=5. It shows the characteristics at OV.

When VDD is 3v and 5v, the characteristic frequencies f1 and f are I
MIIz and 10MHz are 10 times different. This is because the gate lengths of the transistors MIO and M2O and the gate @W are fixed, so the current also increases by about 3 degrees at 5V.

The second conventional example also exhibits similar characteristics and has more output drive stages, resulting in an even larger current increase than the first conventional example. However, it is known that the second conventional example has a wider dynamic range than the first conventional example.

[Problem that the invention seeks to solve]

The above-described conventional operational amplifier has a drawback in that when desired frequency characteristics are to be obtained with a low voltage power supply, power consumption increases significantly as the power supply voltage increases. Conversely, if you create the desired frequency characteristics with a high power supply voltage, operation at a low voltage will sacrifice the characteristics, or in the worst case, it will not work. .

[Means for solving problems]

In order to solve this problem, the operational amplifier of the present invention has %n analog switches, n control terminals for controlling these n analog switches, and n MOS transistors.
) has a block in which the sources and drains of the n MOS transistors are commonly connected, and the gates of each of the n MOS transistors are commonly connected via an analog switch;

It has the feature that it can operate with low power consumption by using a wide power supply voltage range VIJA from low voltage to high voltage by using a control signal in the differential amplification stage and output amplification stage or output drive stage of the g7Aa.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The differential amplification stage includes a pair of Nch MOS transistors Ml and M2 with the same gate length and gate width W,
Pch MOS as a load) U/distor pair M3゜M
The sources of Nch MOS transistors M1 and M2 are commonly connected, and are further connected to the drains of n Nch MOS transistors Mll to Min.

Nine Nch MOS transistors Mll-M
The sources of in are commonly grounded. The output amplification stage consists of n P
The drains of ch gos transistors M31 to M3n are commonly connected to form n Nch MO8 transistors M.
The gates of 21 to M2n are NchMOS transistors Ml
1 to M12, respectively, and connected to respective output terminals 01 of analog switches B1 to Bn, which are made up of switches S1 and 82 and an inverter G1 and have input terminals 11 and I2, an output terminal 01, and a control terminal C1. ing.

The input terminals I2 on the switch Sl side of the analog switches Bl-Bn are each grounded, and the input terminals I2 on the switch Sl side of the analog switches Bl-Bn are grounded, and
The input terminals of l1 are all connected in common, and 206MO
8 transistor M7 and NchMO8 transistor M5.
It is connected to the drain-gate connection of M5 of the bias stage composed of M6.

In addition, n Pch MOS) transistors M31~
The gate of M3n is connected to the analog switches B1 to Bn.
are connected to the output terminals 01 of analog switches Al to An having the same circuit configuration as analog switch A.
One input terminal chip 2 on the switch Sl side of switches 1 to An is connected to the power supply terminal VDD, and the other input terminal chips 1 are all connected in common to form an Nch MOS which is the output of the differential amplification stage.
Connected to the drain side of transistor M2. Analog switches A1-An and analog switches B1-B
The control terminals C1 of n are analog switches A1 and Bl.

A2 and B2. . . . -An and Bn are respectively connected, and each connection point is an external control terminal P1 to Pn that can be externally controlled. CC is a capacitor for applying feedback from the output terminal 3 to the output of the differential amplification stage for phase compensation and compensation.

When the power supply voltage is low, by setting all external control terminals P1 to Pn to a high level and turning on the switch S2 side of the analog switches B1 to Bn, current flows to the NchMO8) transistors Mll to Min and M21 to M2n, respectively. flows. As more current flows, the characteristic frequency of the frequency characteristic extends to a higher range. Furthermore, Nch MOS
) transistors Mll and M21 l! :Pch MO
S) Adjust and design the gate length and gate width W with good DC balance with transistor M31 to create an Nch MO
S) The transistors M12 to Mlna have the same gate length and gate width W as M11, Nch MOS) The transistors M22 to M2n have the same gate length and gate width W as M21, and the Pch MOS transistors M32 to M3n
By setting the gate length and gate width W to be the same as M31,
D regardless of the settings of external control terminals P1 to Pn.
An operational amplifier with good C balance can be realized.

When the power supply voltage is high to a certain extent, the external control terminal can control the flow of current enough to obtain the desired frequency characteristics, thereby preventing unnecessary increases in power consumption due to obtaining excessive characteristics. This makes it possible to optimize power consumption over a wide range of power supply voltages.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. FIG. 2 shows M1 to M7 of the conventional circuit shown in FIG. Mlo, M2O
, M2O, M2O, M2O, M2O, M2O.

It has the same configuration as M2O and CC, but its much 4
four analog switches At, Bl, Xi, Yl and four Nch MOS) transistors Mll, M2
1°M41. M51 and 1 Pch MOS)
It has a transistor M31. The analog switch is
It has a CMOS configuration, and has a transfer gate configuration with two inputs, one output, and two control terminals.

The gate of M2O is also connected to the gate of M41 via an analog switch X1 whose one input is grounded, and M41 and M2O are connected in parallel except for the gate of M41 and the gate of M2O. ing. M51
The relationship between M2O and M21 and the relationship between M21 and M2O are also
The configuration is the same as the connection method of and M2O. The gates of M21 and M2O are also connected to the gates of Mll and MIO, respectively. The gate of M2O is also connected to M31 via an analog switch A1 whose one input is connected to the power supply terminal VDD.

This embodiment corresponds to the case of the brown 1 embodiment in which the number of transistors is n = 2 and each transistor is (n-1) = 1, and the signal at the external control terminal is at a high level. This is an example in which at least a certain amount of current is allowed to flow through the differential amplifier stage, the output amplification stage, and the output drive stage, regardless of whether the current is active or not.

When the control signal from external control terminal P1 is at high level,
4 analog switches AI, Bl.

The internal switch z1 of XI and Yl becomes conductive, and the MOS transistors Mll, M21, M31, M41, M5
1, a bias is applied to each gate. In this state, Mll is connected in parallel with MIO, M21
is connected in parallel with M2O, M31 is connected in parallel with M2O, M4
1 is equivalent to being connected in parallel with M2O, and M51 is equivalent to being connected in parallel with M2O, and since a correspondingly large amount of current flows, the band of frequency characteristics is expanded. With the same power supply voltage, the band changes depending on the control signal, but changes in the power supply voltage also change the current and change the band.

By appropriately selecting the gate lengths and gate widths W of all the MOS transistors in Fig. 8g2 using the above operation, the frequency characteristics as shown in Fig. 6 can be changed to 91. can be expressed.

In Figure 6, when Vop = 5V and the control signal is at a low level, a characteristic with a characteristic frequency band of approximately IMHz is obtained, and when VDD = 3V, the control signal is set to a high level. ), the characteristic frequency is approximately 900kHz
z characteristics can be realized, and when VDn=5V, characteristics close to those when the control signal is at a low level can be obtained.

Furthermore, in the present invention, all the Nch MOS transistors in the above embodiments are Pch MOS transistors,
All Pch MOS transistors are Nch MO8
) Similar characteristics can be obtained in a circuit configuration in which a transistor is used and the voltage relationship between the power supply voltage VDD and the ground is reversed.

〔Effect of the invention〕

As explained above, the present invention provides an operational amplifier configured with 0MO8 having a differential kJJ amplification stage, a power output amplification stage, a differential amplification stage, an output amplification stage, and an output drive stage.
3) Using a set of transistor arrays in which the gates of transistors are connected in parallel through analog switches, the control signal applied to the control terminal of the analog switch provides good frequency characteristics at low power supply voltages and high power supply. This has the effect of realizing an operational amplifier with low power consumption even when voltage is being applied. Particularly, when it is necessary to use the power supply over a wide range of power supply voltages, it is possible to select the optimum power consumption for the desired frequency characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the invention, FIG. 2 is a circuit diagram showing a second embodiment of the invention, and FIG. 3 is a diagram showing the frequency characteristics of FIG. 4 and 5 are conventional circuit diagrams, and FIG. 6 is a diagram showing the frequency characteristics of the circuit of FIG. 4 or 5. AI, Bl, Xi, Yl-----Ana Ol'
Xyyf, C1... Control terminal of analog switch sCC... Capacity, Ml, M2. M11~Mi
n, M21-M2n. M5. M6, MIO, M2O, M2O, M41, M
2O. M51. M2O...Nch MOS) transistor, M3゜M4, M31~M3n, M7, M
2O, M2O...PchMO5) transistor,
Nl, N2. Gl... Inverter, 01...
...Analog switch output, Pl~Pn...
・External control terminal, S, 100...-0 MO8 configuration switch control terminal, 31.82...Switch, Z
1. Z 2------0MO8II formation OX switch, Il. Engineering 2... Anakyo Gusui, chi input, vDD...
...Power supply voltage terminal, 1.2...Operation amplifier input, 3...Operation amplifier output. Agent: Susumu Uchihara, patent attorney Figure 1 Figure 6

Claims (1)

[Claims] In an operational amplifier composed of MOS transistors consisting of a differential amplification stage and an output amplification stage, or a differential amplification stage, an output amplification stage, and an output drive stage, the differential amplification stage and the output amplification stage or the output drive stage are used. The gates of all or some n MOS transistors are connected in parallel via n analog switches, and the n sources and drains of the MOS transistors are connected in parallel. An operational amplifier characterized in that it is a block and the n analog switches can be controlled by n control terminals.