JPS59149408A - Differential amplifier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplifier consisting of two inputs connected to a two-input terminal source and two outputs connected to a subsequent circuit, and requiring no offset voltage.

In an ideal differential amplifier, the output voltage should be zero when the voltages at the two input terminals are equal. However, in an actual differential amplifier, even if the voltages at the two input terminals are equal, a voltage is generated at the output, and the output voltage can only be reduced to zero by supplying a correction voltage to one of the two input terminals. . This correction voltage is called an offset voltage.

MOS(Metal Oxide 5eIlicond
uctor) and 0MO8(Complementary
Metal Oxide Sem1conducto
It is known that the offset voltage of a differential amplifier designed and manufactured by the r) technology is about an order of magnitude larger than the offset voltage of a differential amplifier similarly designed by the Heibora technology. This offset voltage is mainly due to the difference in threshold voltage of the 2411 transistors of the differential power stage. Furthermore, asymmetry between load elements connected to the transistors of the differential input stage also has a large effect on the offset voltage. A differential amplifier manufactured by CMOS technology with a gate structure made of polycrystalline silicon requires an offset voltage of about 10 to 20a+V. For this reason, the range of applications for this type of differential amplifier is limited to cases where the presence of offset voltage is not a major problem, such as in a gain of 1 buffer, and cases in which the presence of offset voltage is not a major problem, such as in a gain of 1 buffer, or
This is limited to cases where damage compensation is possible.

As a solution to reduce the offset voltage of such a differential amplifier, the so-called CAZ (Gommutat
ing Auto-Zero) technique is known, in which the offset voltage is measured, stored in a capacitor, and used for compensation. An example of this is the Intersil ICL7E150 operational amplifier, which requires two external capacitors with a capacitance of 0.01 to 0.1 μF to store the compensation voltage, but achieves low offset voltage and low drift values. There is.

If this solution were to be used in an integrated circuit, the capacitor would have to be integrated into the integrated circuit, creating a new drift problem. This is because the leakage current that causes discharge of such capacitors is temperature dependent and varies by at least an order of magnitude from one integrated circuit manufacturing loft to another. Considering the limited space on the semiconductor surface of an integrated circuit, such a capacitor can be
It is not possible to increase the capacitance to 0 pF or more.

Therefore, even a small leakage current causes a large charge loss, resulting in an offset voltage.

Therefore, an object of the present invention is to provide a differential amplifier that does not require an offset voltage and can be integrated without problems.

This invention will be explained below.

The present invention relates to a differential amplifier comprising two outputs each connected to a two-input terminal source by a first switching means, and two outputs each connected to a subsequent circuit by a second switching means, The first and second switching means are clocked by a switching clock generator such that the first input is connected to the first input voltage source, the second input voltage is connected to the second input terminal source, and the subsequent circuit is connected to the first input voltage source.
output, or the first input is connected to the second input terminal source, the second input is connected to the first input voltage source, and the subsequent circuit is connected to the second output. Furthermore, a low-pass filter for removing fluctuations in output due to switching frequency is connected between the output terminal of the second switching means and the subsequent circuit.

This invention is based on the following facts.

For example, in a differential amplifier configured with MOS transistors, if there is some asymmetry within the differential amplifier, such as when the threshold voltage of the transistor in one input stage is different from the threshold voltage of the transistor in the other input stage. For example, some offset voltage will occur. Here, if we change the element causing the asymmetry, that is, in the above example, if we replace the MOS transistors connected to the two input stages of the differential amplifier, the same asymmetry will occur. The results are the same in magnitude but opposite in polarity. Such an exchange results in offset voltages of equal magnitude but different polarity. Therefore, by periodically switching the connection between the two input terminal sources and the two outputs and the subsequent circuit, an offset state with changing polarity can be obtained, but this offset voltage cannot be passed through a low-pass filter. For example, if equal input voltages are supplied to the input stage of the differential amplifier, the output voltage of the low-pass filter will be zero. It is possible to add two switching means and a low-pass filter to a conventional differential amplifier, and it is also possible to switch the circuit elements that cause asymmetry in the above-mentioned sense. A differential amplifier can also be configured.

In an NSL embodiment of the invention, the first switching means includes a first controllable switch connecting the first input of the differential amplifier to the first input power source; a second controllable switch connecting the second input voltage source; a third controllable switch connecting the second input of the differential amplifier to the second input voltage source; and a third controllable switch connecting the second input of the differential amplifier to the second input voltage source; a fourth controllable switch connecting the second input to the first input voltage source, the second switching means connecting the output terminal to the first output of the differential amplifier; Possible swing. And in this embodiment, the switching clock generator is the first . ``directly to the control inputs of the third and fifth switches, and the second. The switching pulses supplied via the inverter to the control inputs of the fourth and sixth switches are generated with a duty cycle of 50%. Such a differential amplifier is fabricated with a common IC design, and the switching means and low-pass filter can be added as external circuit elements.

Other embodiments of the invention are all monolithically integrated, consisting of two transistors each with a control terminal connected to one of the inputs of the differential amplifier, with the main path of each transistor connecting the load and the two transistors. the transistor forming the output and the node between the load, the control terminal of the first transistor being connected to the first input terminal via the main path of the switching transistor of the LSL; The switching transistor is connected to a second input terminal of the differential amplifier via the main path, and the control terminal of the second transistor is connected to the second human power terminal via the third switching transistor main path. , is connected to the first input terminal of the differential amplifier via the main path of the fourth switching transistor, and the output terminal is connected to the first output via the main path of the fifth switching transistor. , are connected to the second output of the differential amplifier via the main path of the sixth switching transistor. And the first. The control terminals of the third and fifth switching transistors are directly connected to the output of the switching clock generator 1, the second . The control terminals of the fourth and sixth switching transistors 2 are connected to the output of the switching clock generator via an inverter.

Furthermore, in a special embodiment of the invention, two
one transistor is each coupled to a load formed by first and second load transistors. and a node between the second transistor and the second load transistor forms a first output of the differential amplifier, and a node between the first transistor and the first load transistor forms a second output of the differential amplifier. is forming the output of Control terminals of the first and second load transistors are connected to a common circuit node that is connected to one of the outputs of the differential amplifier. This common circuit node is connected to the first output via the main path of the seventh switching transistor and to the second output of the differential amplifier via the main path of the seventh switching transistor. . The control terminal of the seventh switching transistor is connected to the output of the switching clock generator via an inverter, and the control terminal of the eighth switching transistor is directly connected to the output of the switching clock generator.

Next, the present invention will be explained with reference to the drawings.

First, in order to explain the basic principle of the present invention, the circuit configuration of a conventional differential amplifier is shown in FIG.

This differential #! The width transducer has an inverting input El and a non-inverting input E2.
and output A. A first input voltage VIN- is applied between the inverting input E1 and the supply voltage line vss. The second input terminal VIN- is applied between the non-inverting input terminal E2 and the supply voltage line VSS. Then, the output voltage hr is generated between the output terminal A and the supply voltage line vss. The differential amplifier includes two MOS type amplification transistors Ml and N2.
, whose gates are connected to an inverting input E+ and a non-inverting input E2, respectively. Furthermore, MO9 type load transistors M3 and N4 are connected in series with amplification transistors M1 and 'M2, respectively. The load transistors M3 and N4 are connected to the supply voltage MVSS, while the amplifying transistors N1 and N2 are connected via the current source 1 to the supply voltage line vDD. Then, the gates of load transistors M3 and N4 are connected to each other, and the amplification! - Connected to the connection point of transistor M1 and load transistor M3.

Here, assuming that the amplification transistors old and N2 have completely equal characteristics, and the load transistors N3 and N4 have completely equal characteristics, when no differential input voltage is applied, that is, VIN- “When VIN-,
The output voltage is vou'r0=VGS(N3.N4). Here, VGS (N3, 84) is the voltage between the gates of load transistors N3 and N4 and the supply voltage line VSS.

If there is some difference in terms of threshold voltage between the amplifier transistors l and N2, while the load transistors N3 and N4 are still perfectly equal, the output voltage will be:

, vOUT "vOUTo +AO" (vTMI-
vTM2)・・・・・・・・・(1) Here, VOUTo is the output voltage obtained when the characteristics of all transistors are completely equal, Ao is the open loop gain, and (VTMI-VTM2) is the output voltage obtained when the characteristics of all transistors are completely equal. N
1 and N2. For example, Ao = 100. (VTMI-V7H2)=5mV
Then, the output voltage VOUT is VOUT0 + 500mV
becomes.

Mata, vTM2 = 5mv in vTMl, Tsumari (VTMI
-VTM2)"-5Iv, the output voltage VOUT is V
It becomes OUTo-500mV.

The drains of the amplification transistor old and N2 are connected,
Even if the gates are exchanged as shown in Figure 2, that is, the gate of the old amplifying transistor is connected to the inverting input El, the gate of the amplifying transistor M2 is connected to the non-inverting input E2, and the gate of the old amplifying transistor is connected to the inverting input E1. Similar results can be obtained by connecting the drain of the amplifier transistor M2 to the output terminal A and connecting the drain of the amplification transistor M2 to the common gate of the load transistors M3 and N4.

This circuit provides the following output voltages:

VOUT"vOUTo-"°(vTMI-VTM
2)・・・・・・・・・(2) As can be seen from the above equations (1) and (2), if there is some asymmetry between the amplification transistors Ml and M2,
In the circuit shown in FIG. 1 and the circuit shown in FIG. 2, the output voltages differ in polarity but change by the same amount. Asymmetry includes not only the difference between the threshold voltage of the old amplification transistor and the threshold voltage of the amplification transistor M2, but also all kinds of asymmetries that cause offset errors9, for example, due to the geometry of the transistor structure. This includes differences in gain and differences in gain.

Taking advantage of this fact, the present invention periodically switches the two outputs of the differential amplifier to periodically reverse the polarity of the output offset voltage. This output signal, whose polarity changes periodically, is averaged by a subsequent low-pass filter. In the case of two differential amplifiers, when no input signal is applied or when equal input signals are applied, the output voltage of the low-pass filter becomes zero, and in this way, the offset error is removed. That will happen. In order to prevent periodic switching of the output of the differential amplifier from periodically changing the polarity of the output signal, the input stage is also switched periodically. In other words, the input is also switched in synchronization with the switching of the output. Note that switching noise in the input signal that may be caused by this switching is removed by a low-pass filter.

FIG. 3 is a circuit configuration diagram of an embodiment in which the present invention is applied to a conventional differential amplifier [IV to eliminate offset errors, and the conventional differential amplifier DV has an inverting input El
, non-inverting input E2. It consists of a non-inverted output A1 and an inverted output A2. Four control switches Sl, S2 . S3 and S4c, differential amplifier DV (7) 2 human power El and E2 and input voltage terminal Ut
and U2. And the inverted input E
1 is connected to the first input voltage terminal Ul via the switch Sl, and - is connected to the second input voltage terminal U2 via the switch S2. Non-inverting input E2 is switch S
3 to the second input terminal terminal U2, and
It is connected to the first input terminal U1 via the switch S4.

A series connection of control switches S5 and S6 as second switching means and a low-pass filter TP is connected between the two outputs of the differential amplifier and the subsequent circuit terminal Z. The non-inverting output A1 of the differential amplifier Dv is connected to the output terminal O of the second switching means via a switch S5, and the inverting output A2 of the differential amplifier DV is connected to the output terminal O via a switch S8. . A low-pass filter TP is connected between the output terminal O of the second switching means and the subsequent circuit terminal Z.

Switch S1. S3. and S5 or main switch S2. S
Clock generator C generates switch pulses with a duty cycle of 50 percent so that S4 and S6 are alternately conductive. The frequency of the clock is set to be sufficiently higher than the frequency of the input signal to be amplified by the differential amplifier. For example, assuming that the frequency of the input signal is in the range of DC levels to audio frequencies, it is desirable that the clock frequency be on the order of several 100 KHz. j and the input signal to be amplified is zero,
At the subsequent circuit terminal Z, an output DC voltage VOUT·0 is obtained. In other words, any asymmetry that would cause an offset error in a conventional differential amplifier Dv will not appear at the output due to the circuit added by application of the present invention.

FIG. 4 is an equivalent circuit diagram of the circuit portion surrounded by a broken line in FIG.
By combining O and the low-pass filter TP, the differential amplifier DV from which the offset error has been removed will operate in the same way as a differential amplifier without the offset error. In this differential amplifier, an inverting input is applied from an input voltage terminal Ul, and a non-inverting input is applied from an input voltage terminal U2.

The output is output from the subsequent circuit terminal Z. The output voltage obtained at the subsequent circuit terminal Z of this equivalent circuit diagram is no longer distorted by the offset error.

FIG. 5 is a circuit configuration diagram of another embodiment of the present invention, in which a switching means configured to be used in a monolithic integrated circuit and to which the invention of the day is applied is also integrated into a differential amplifier circuit. It is becoming more and more popular. The circuit configuration of this embodiment is a series connection of an amplification transistor TI and a load transistor LTI, and a parallel connection of a series connection of an amplification transistor T2 and a load transistor LT2. It is connected to the first voltage supply line VDD via the current source 2 on the side thereof, and connected to the second voltage supply line Vss on the side of the load transistors LTI and LT2. Amplifying transistors T1 and T2 have their drains connected to the drains of load transistors LTI and LT2, respectively, and gates of load transistors LTI and LT2 are both connected to connection point X.

The first input voltage terminal U1 has an inverted input voltage VIN−.
is applied, and the non-inverted input voltage VIN is applied to the second input terminal. Then, the output voltage VOUT of the differential amplifier is outputted to the output terminal O.

The gate terminals of the amplification transistors TI and T2 are connected to a first output AI and a second output specific to the differential amplifier composed of the amplification transistors TI and T2 and the load transistors LTl and LT2.
It is configured by output A2.

The connection point between the amplification transistor T2 and the load transistor LT2 is the first output AI specific to the differential amplifier, and the connection point between the amplification transistor T1 and the load transistor LTI is the second output A2 specific to the differential amplifier.

The amplification transistor 71 and its gate are connected to the input terminal Ut via the first switching transistor STI, and to the input voltage terminal U2 via the second switching transistor ST2. Similarly, the gate of the amplification transistor T2 is connected to the input terminal U2 via the third switching transistor ST3, and the gate of the amplification transistor T2 is connected to the input terminal U2 via the third switching transistor ST3.
The switching transistors 8 and 4 are connected to the input voltage terminal [1. The output terminal 0 is connected to the amplification transistor T via the fifth switching transistor ST5.
2 and the load transistor LT2, and is connected to the amplification transistor Tl and the load transistor LT via the sixth switching transistor ST8.
connected to the common drain of I. , the common gate terminal X of the two load transistors LTI and LT2 is connected to the seventh
It is connected to the common drain of the amplification transistor T2 and the load transistor LT2 via the switching transistor ST7, and is also connected to the common drain of the amplification transistor T1 and the load transistor LTI via the eighth switching transistor ST8. There is.
- and the two amplification transistors TI and T2 are each P-channel 80S5 transistors, and the load transistors LTI and LT2. switching transistor S
TI to ST8 are N-channel MO3 type transistors.

S-(, pinching transistor STI, Si2, S
The gate terminals of r1 and Si2 are directly connected to the clock line CLK;
, Sr1, and the gate terminals of Sr1 and Sr1 are connected to the clock line CLK via an inverter (2). A periodic switching pulse with a duty cycle of 50 percent is applied to the switching transistor by the a-+7 line CLK. In this embodiment, at the clock time tl shown in FIG. 5, the switching transistors ST2, Sr1. Sr1 and Sr1 become conductive, and switching transistors ST1, Si2 . Sr1 and Si
2 becomes conductive.

The switching transistors 5TI-Sr1 switch between the amplification transistors T1 and T2, the inverting input voltage terminal Ut, and the non-inverting input voltage terminal U2! and STB are the common drain terminals of the amplification transistor T1 and the load transistor LTI, or the common drain terminal of the amplification transistor T2 and the load transistor LT.
The connection between the common drain terminal of 2 and the output terminal O is switched. Switching transistor S? ? and STB
switches the connection between the common gate terminal X of the two load transistors LTI and LT2 and the drain terminal of the load transistor LTI or LT2.

By the switching operation of the switching transistor, the circuit shown in FIG. 5 is switched to the circuit shown in FIG. 1 or the circuit shown in FIG. 2, but in addition to this switching,
The connection between the common gate terminal X of load transistors LTI and LT2 and the drain terminal of load transistor LTI or LT2 is switched. I mean.

The assumptions made in the circuits of FIGS. 1 and 2.

The asymmetry, or asymmetry, is only caused by the two amplifying transistors, while the assumption that the characteristics of the two load transistors are completely equal is not realistic; in practical applications, even between the two load transistors Similarly, asymmetries exist. The resulting asymmetry is then compensated for by periodic switching of the load transistor, just as the asymmetry due to the amplification transistor is compensated for by its periodic switching.

In the embodiment shown in FIG. 5, each transistor is of a unipolar type such as an N-channel MOS or a P-channel MO9, but it is also possible to use a bipolar type transistor.

Furthermore, the amplifying transistors TI and T2jf transistors may be replaced with double-coupled Darlington-connected transistors or cascade-connected transistors.

In addition, when it is necessary to lower the supply voltage or reduce power loss, or when you want to obtain a large common-mode signal input voltage range, switching transistor STI
~5TI3 may be replaced with a mutually complementary transistor pair.

The clock pulse on the clock line CLK must have a duty cycle of 50% - but no matter how small the deviation from this ideal value is, the offset voltage v = v ・a - tJ ......
...(3) OS O20t2 is generated. Here, VO50 is the offset voltage without compensation, tl is the low level clock time, t2
By using a zero-frequency divider circuit in which the clock time is a high level, it is possible to easily obtain a clock signal with a period having an asymmetry of less than 0.1%.

When a differential amplifier and another amplifier are connected in series, and the offset error is compensated for by applying the method of the present invention to the differential amplifier in the front stage, but no compensation is applied to the amplifier in the rear stage, To prevent offset errors caused by the threshold voltage of the subsequent amplifier, the voltage gain of the compensated differential amplifier should be as large as possible.
This is because the higher the gain of the differential amplifier, the lower the input compensation voltage required to be supplied to the preceding differential amplifier to compensate for the offset error caused by the threshold voltage of the subsequent amplifier. It is.

Considering this, a two-stage differential amplifier with an offset-compensated differential input stage and an uncompensated single-power amplifier stage has an offset value that is at least two orders of magnitude lower than a conventional circuit without offset compensation. It can be configured to have only one. Therefore, the offset voltage value is 100
It becomes possible to suppress the ILV or below. Since the drift due to temperature decreases on the order of several V/"C!, the drift value adjusted by temperature can be reduced to several V/"C at most.

As an application example of the offset-compensated differential amplifier to which this invention is applied, the so-called band gap voltage reference (band gap voltage reference) shown in FIG.
nce) circuits. Such a reference source is 1.2
This is a very stable constant voltage source that generates a reference output voltage of 5V, and a description of its circuit configuration and functions will be omitted. Such a bandgap voltage reference circuit consists of amplifier transistors Old and M2 and load transistors M3 and M4.
It includes a differential amplifier of the type shown in FIG. In this circuit, the deviation of the output voltage vGo from the nominal value is mainly caused by the input offset voltage of the differential amplifier. Since the difference in base-emitter voltage, VBE, between transistors Ql and Q2 is only 55 mV, an offset voltage of 10 mV causes a significant shift in the output voltage vGo. Generally speaking, in such a bandgap voltage reference circuit, the output voltage VGo varies from 1.2V to about IO percent, and the temperature coefficient is ±
It is about 500 ppm/"0.

Instead of a differential amplifier with transistors M and I4,
For example, by using a compensated differential amplifier according to the present invention as shown in FIG.
“It can be kept below O.

As described above, according to the present invention, it is possible to obtain a differential amplifier that satisfactorily satisfies the first objective and advantages described above. Although the present invention has been described above with reference to specific examples, it is clear that many variations and modifications can be made to the present invention. Therefore, all variations and modifications that fall within the scope of the claims are intended to be included in the present invention.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional differential amplifier, Fig. 2 is a circuit diagram of a differential amplifier in which the wiring of this differential amplifier is changed, and Fig. 3 is an implementation in which the present invention is applied to a conventional differential amplifier. 4 is an equivalent circuit diagram thereof, FIG. 5 is a circuit diagram of another embodiment of the present invention, and FIG. 6 is a diagram showing an application example of a conventional differential amplifier. El...inverting input, E2...non-inverting input, A...
Output terminal, Ml, M2...IllO5 type amplification transistor, ■...Current source, M3, 84...Load transistor, mouth V...Differential amplifier, ↑P...Low-pass filter, Z... ...Subsequent circuit terminal. Applicant's agent Yuzo Yasugata

Claims (1)

[Claims] (1) A difference consisting of a first input and a second human power connectable to a first input voltage source and a second input terminal source, and a first output and a second output connectable to a subsequent circuit. In the dynamic amplifier circuit, each of the first input voltage source and the second input terminal source is connected to either the first input or the second input terminal by a first switching means, and the subsequent circuit is connected to the second input voltage source by the second switching means. is connected to either the first output or the second output, the first switching means and the second switching means are switched by a switching clock generator, and the first input is connected to the first output or the second output. a first input voltage source, such that the second human power is connected to the second input terminal source and the subsequent circuit is connected to the first output; an input terminal source, the second human power is connected to the first input terminal source, and the preceding and subsequent circuits are connected to the second output, and for eliminating fluctuations in the output due to switching frequency; A differential amplifier characterized in that a reduction filter is connected between the output terminal of the second switching means and the subsequent circuit. (2) the first switching means includes a first control switch connecting the first input to the first input voltage source; and a second control switch connecting the first input to the second input terminal source. a third control switch connecting said second human power to said second input terminal source; and a third control switch connecting said second human power to said second input terminal source;
- a fourth controlled switch connecting to a distribution 1 input voltage source, said second switching means comprising a fifth controlled switch connecting said output terminal to said first output;
a sixth control switch connecting the output terminal to the second output, wherein the switching clock generator generates a switching pulse with a duty cycle of 50 percent to connect the first control switch and the third control switch. and the fifth control switch directly, and the second control switch, the fourth control switch, and the sixth control switch are controlled via an inverter. Differential amplifier. (3) A first transistor TI, a first load connected in series with the first transistor TI, a second transistor, and a second load connected in series with the first transistor TI; Control terminals of the second transistor are connected to the first input and the second input, respectively, a connection point of the first transistor and the first load becomes the first output, and a control terminal of the second transistor and the second In the differential amplifier circuit in which a connection point of a load is the second output, a control terminal of the first transistor is connected to the first input voltage source via a switching transistor serving as the first control switch. and is connected to the second input voltage source via a switching transistor as the second control switch, and a control terminal of the second transistor is connected via a switching transistor as the third control switch. The second input terminal is connected to the source, and is connected to the first input voltage source via a switching transistor as the fourth control switch, and the output terminal is connected to the switching transistor as the fifth control switch. connected to the first output via the sixth control switch, and connected to the second output via a switching transistor serving as the sixth control switch;
control terminals of a switching transistor, a third switching transistor and a fifth switching transistor are directly connected to the output of the switching clock generator, and the second switching transistor;
3. A differential amplifier according to claim 2, wherein a fourth switching transistor and a sixth switching transistor are connected to the output of the switching clock generator via the inverter. (4) The first load of the first transistor is the first
a load transistor, a second load of the second transistor is a second load transistor, and a second load transistor of the second transistor;
The connection point between the transistor and the second load transistor is the first output;
The connection point of the load transistor is the second output, and the control terminals of the first load transistor and the second load transistor are connected to a common circuit node connected to one of the first output or the second output. In the connected differential amplifier circuit, the common circuit node is connected to the first output via the seventh switching transistor and to the second output via the eighth switching transistor. a control terminal of the seventh switching transistor is connected to the output of the switching clock generator via the inverter, and a control terminal of the eighth switching transistor is connected to the output of the switching clock generator. 4. A differential amplifier according to claim 3, which is directly connected. (5) The yarn amplifier according to claim 3 or 4, wherein all transistors used are MO9 type transistors. (6) The differential amplifier according to claim 5, wherein the first transistor and the second transistor are P-channel MOS transistors, and the other transistor is an N-channel MOS transistor. (7) The differential amplifier according to claim 5, wherein the first transistor and the second transistor are N-channel MO3 type transistors, and the other transistor is a P-channel MOS type transistor. (8) Each of the first switching transistor to the eighth switching transistor is Cl4O5
Claim 5 consisting of a type transistor pair
Differential amplifier as described in section. (9) The differential amplifier according to any one of claims 3 to 8, wherein each of the first transistor and the second transistor is a Darlington connection transistor. (lO) The differential amplifier according to any one of claims 3 to 8, wherein the first transistor and the second transistor are each formed of a cascade-connected transistor. (11) The differential amplifier according to any one of claims 1 to 10, wherein all the components used are monolithically integrated.