JPH01117781U - - Google Patents
Info
- Publication number
- JPH01117781U JPH01117781U JP870288U JP870288U JPH01117781U JP H01117781 U JPH01117781 U JP H01117781U JP 870288 U JP870288 U JP 870288U JP 870288 U JP870288 U JP 870288U JP H01117781 U JPH01117781 U JP H01117781U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- port
- logic
- input port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001629 suppression Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案の一実施例を、遅延回路５段
の場合について示す図、第２図は従来のこの種装
置を遅延回路５段の場合について示す図である。
図において１ａ，１ｂ，１ｃ，１ｄ，１ｅは遅
延回路、２ａ，２ｂ，２ｃ，２ｄ，２ｅ，２ｆ，
７ａ，７ｂ，７ｃ，７ｄ，６，９は比較器、３ａ
，３ｂ，３ｃ，３ｄ，８は計数回路、４は制御回
路、５はセレクタである。なお、図中同一符号は
同一または相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention in the case of five stages of delay circuits, and FIG. 2 is a diagram showing a conventional device of this type in the case of five stages of delay circuits. In the figure, 1a, 1b, 1c, 1d, 1e are delay circuits, 2a, 2b, 2c, 2d, 2e, 2f,
7a, 7b, 7c, 7d, 6, 9 are comparators, 3a
, 3b, 3c, 3d, and 8 are counting circuits, 4 is a control circuit, and 5 is a selector. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
接続された第１〜Ｎ（Ｎは３以上の奇数）の遅延
回路と、第１と第２の入力ポートを有し、第１の
入力ポートに前記第ｉ（ｉ＝Ｎ＋１２）の遅延回
路出力を入力し、第２の入力ポートに前記第ｎ（
１≦ｎ≦Ｎ，ｎ＝ｉ）の遅延回路出力を入力し、
第１の入力が第２の入力より小さい場合、論理“
１”を出力するＮ−１個の比較器と、Ｎ−１個の
入力ポートを有し、各入力ポートに前記Ｎ−１個
の比較出力を入力し、入力が論理“１”である入
力ポート数を計数し、その値を出力する計数回路
と、第１と第２の入力ポートを有し、第１の入力
ポートに前記計数回路出力を入力し第２の入力ポ
ートにあらかじめ設定された値Ｋを入力し、第１
の入力が第２の入力より大きい場合、論理“１”
を出力する比較器を備えたことを特徴とする雑音
抑圧装置。 It has first to N (N is an odd number of 3 or more) delay circuits connected in series that introduce an input signal, delay it, and output it, and first and second input ports, the first input port being a first input port. The output of the i-th (i=N+12) delay circuit is input to the output port of the i-th (i=N+12) delay circuit, and the output of the n-th (i=N+12)
Input the delay circuit output of 1≦n≦N, n=i),
If the first input is less than the second input, the logic “
an input having N-1 comparators that output "1" and N-1 input ports, each input port inputting the N-1 comparison outputs, and the input being a logic "1"; It has a counting circuit that counts the number of ports and outputs the value, and a first and second input port, the output of the counting circuit is input to the first input port, and a preset value is set to the second input port. Enter the value K and select the first
logic “1” if the input of is greater than the second input
A noise suppression device characterized by comprising a comparator that outputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP870288U JPH01117781U (en) | 1988-01-26 | 1988-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP870288U JPH01117781U (en) | 1988-01-26 | 1988-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01117781U true JPH01117781U (en) | 1989-08-09 |
Family
ID=31214810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP870288U Pending JPH01117781U (en) | 1988-01-26 | 1988-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01117781U (en) |
-
1988
- 1988-01-26 JP JP870288U patent/JPH01117781U/ja active Pending
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