JPH01120832A - Formation of hood pattern - Google Patents

Abstract

PURPOSE:To form a pattern at a setting layer and obtain the pattern with high accuracy, by forming a mask layer at side walls of a dummy layer and making the surface region of the above dummy layer form a setting layer by light irradiation, thereby removing the dummy layer as well as non-setting layers in the mask layer. CONSTITUTION:A mask layer 14 is provided at side walls of a dummy layer 13 that is treated most accurately and light irradiation allows the mask layer 14 to form a uniform setting layer 14a having a desired thickness. Then the setting layer 14a and a gate metallic film 10 formed on the setting layer are removed by a lift-off process and the like. In this way, a part of the gate metallic film 10 remains on mortised parts 11 and as this metallic film acts as a gate electrode 12, it is possible to form the electrode which has highly accurate dimensions and a desirable sectional form. In this way, since a highly accurate gate electrode 12 is formed by taking advantage of a pattern with hood 18 made by the setting layer 14a which is formed with high accuracy, its excellent characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a method of forming an eave pattern to serve as a lift-off mask.

[Conventional technology]

As semiconductor devices progress, integrated circuits (Integrated C!
As the demand for IT (hereinafter referred to as IC) increases,
To achieve this, compound semiconductors, especially GaAs1I using gallium arsenide (hereinafter referred to as GaAa), are used.
Expectations for O are rising. In recent years, this GaAs I
Research and development at OK is active, and efforts are being made to improve and develop the device structure and manufacturing process in various fields to achieve higher performance and higher quality. Transistors formed in 0 GaAa I O Improving the uniformity of the electrical characteristics and reliability of the FA can only be achieved by optimizing the FA fabrication process. For example, GaA used in wideband amplifiers, high-power amplifiers, or phase shifters isobaric.
sAnalog ICs usually include a Schottky junction field effect transistor (M
etal-8enriaonduotor Field
-Effect Transistor: Hereinafter, MES
F'E'r) is formed. In this device, a recess is formed in a part of the active layer on a semi-insulating GaAa substrate in order to suppress the influence of the surface depletion layer and obtain the desired drain current characteristics, and a lift-off method is applied to the main surface of the active layer. A Schottky barrier contact gate electrode is provided on both sides of the gate electrode, and ohmic contact source and drain electrodes are provided on both sides of the gate electrode on the active layer without the trench. The electrical characteristics of such a MES FET depend on the processing precision of each of the electrodes, and the quality of the characteristics is determined by how well the lift-off mask for forming each electrode can be formed with good controllability. . In other words, each of the above electrodes has its own structure formed by using the pattern structure formed on the resist that serves as the lift-off mask, and the dimensional accuracy and cross-sectional shape of the resist pattern are Become something. Therefore, in order to make the FET properties uniform, improve performance, etc., it is essential to improve the precision of the resist pattern processing.

By the way, 1. Figure 5 shows an MES with recessed gate #I in a semiconductor device formed using a conventional pattern.
FIG. 3 is a diagram showing the structure of an FET section. In the figure, (1) is a semi-insulating substrate (hereinafter referred to as the substrate) made of GaAs etc.
, 12) are N conductivity type (hereinafter referred to as NW) active layers formed on this substrate (1), and (3) and (4) are ohms provided oppositely on this active layer (2). (5) is a recess formed in the active layer (2) approximately in the center between the source and drain electrodes (3) and (4);
(6) is a gate electrode made of a Schottky electrode provided on this recess (5), and (7) is this gate polarization (
6) This is the fluff on the corners at both ends of the machined surface.

Regarding the conventional MES FET configured in this way,
The forming force method will be explained by taking the gate electrode (6) portion as an example.

Figures 6(a) to (C) show gate 1 according to the conventional pattern.
It is a figure which shows the main formation process of a pole (6). This thing is
First, silicon (S
l) Perform selective ion implantation using ions or the like to form an N-type operating layer (2). After that, for example, a positive type resist (8) is spin-coated on the entire surface to a predetermined thickness,
Predetermined patterning is performed by a phosphorography process to form an opening (9) pattern in the resist (8). Here, in the predetermined patterning, first, the substrate (1) is exposed to ultraviolet light or the like through a photomask.
) is immersed in a chlorobenzene solution for a predetermined time to harden a region of the resist (8) extending from the cut surface to a predetermined thickness. This chlorobenzene treatment is for controlling the shape of the opening (9) pattern, and the processed shape is controlled by utilizing the difference in solubility during the development process in the subsequent step. After that, when the exposed portion of the resist (8) is selectively removed by developing, an opening (9) having a gently tapered cross-sectional shape is formed.
will be formed (Fig. 6 (c))).

Next, a wet etching process using a hydrogen peroxide mixture or the like is performed to selectively remove the exposed portion of the active layer (2) through the opening (9) to a predetermined depth, thereby changing the crystal orientation of the active layer (2). In this case, an inverted mesa-shaped recess (5) is formed. This excavation (5) is caused by the fact that the coating on the resist edge portion at the bottom of the opening (9) is thin and easily etched, and the processing has progressed inward from the mask layer formed by the resist (8). , there is a so-called large undercut state, and the opening is the opening (
9). A gate metal film (LI) made of a Schottky electrode material such as titanium, molybdenum, and gold (aluminum with Ti/MoaAu) is deposited on the entire surface of this bale to a predetermined thickness using a vacuum evaporation method or the like (Fig. 6). (b)).

Next, the resist (8) and the gate metal film Q (l) thereon are removed by a lift-off method. As a result, the gate metal film (
A gate electrode (6) is formed so that a portion of II remains. This gate electrode (6) has a protrusion-like shape, with a portion of the gate metal film nl remaining on the side surfaces of the opening (9) in the resist (81) at both ends of its main surface. (Figure 6 (C))

In this way, the resist (8) is used as a lift-off mask, and the gate electrode (6) is formed using the opening (9) pattern structure formed therein.0 [Problem to be Solved by the Invention] [Point] The conventional method for forming a pattern to be used as a lift-off mask is as described above. A chlorobenzene immersion treatment is carried out, and then the exposed portions of the resist (8) are selectively removed by development to form an opening (9) pattern in a predetermined shape in the resist (8). That is, a hardened layer is formed on the surface layer of the resist (8) by chlorobenzene treatment, and the solubility between the hardened layer and the non-hardened layer is made different during development, and the thickness of the hardened layer is The cross-sectional shape of the opening (9) pattern was controlled by adjusting the width of the opening (9).This method is easily affected by the temperature of the immersion liquid, the state of deterioration, the processing time, environmental conditions, etc. The opening (9) allows the resist (8) to form a hardened layer of a predetermined thickness with good stability and has the desired dimensional accuracy and cross-sectional shape.
The pattern was not easy to control. Therefore,
The above-mentioned opening (9) pattern is often formed in a gentle taper shape as in this case, and the gate electrode (6) obtained using this pattern has an uneven bottom surface dimension. The problem was that large protruding fluffs (7) were formed on both ends of the main surface. Therefore, in addition to the problem that the gate length fluctuates and the desired electrical characteristics of the transistor cannot be obtained with good reproducibility, the above-mentioned fuzz (7) causes d-field concentration and short circuits.
Alternatively, there is one problem in that it may have problems such as being damaged and causing foreign matter, and the performance may be impaired.

This invention was made to solve the above-mentioned problems, and aims to provide a method for forming an eaves pattern that can be formed into a desired shape with good reproducibility and achieve high performance. Means for Solving the Problems] The method for forming an eaves pattern according to the present invention covers a dummy layer provided on a semiconductor substrate, patterns the formed resist, and leaves a part of the resist. a first step of forming a mask layer on the side wall of the dummy layer; a second step of irradiating light to form a hardened layer over a predetermined thickness from the surface of the mask layer; and removing the dummy layer. , and then a third step of selectively removing the non-hardened layer of the mask layer to obtain the eaves made of the hardened layer.

[Effect]

The dummy layer in the present invention is formed with good controllability, and the opening in the mask layer where the dummy layer is removed is made uniform and has a desired cross-sectional shape. Moreover, the light irradiation for curing the mask layer from the surface to a predetermined thickness has the function of forming a cured layer uniformly on the mask layer with good reproducibility.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Note that the description of parts that overlap with the description of the conventional technology will be omitted as appropriate. FIG. 1 shows the structure of a semiconductor device formed according to an embodiment of the present invention. It is a figure showing a structure. In the figure,
(1) to (4) are the same as the conventional ones, (B) is a recess formed on the operating layer (2), and (2) is a shot key provided on this recess (B). The gate electrode is composed of an electrode and has the same structure as that shown in FIG. 5, but the shape of the recess (b) and the gate electrode (2) are different.

Hereinafter, the gate electrode (6) portion shown in FIG. 1 will be explained as an example. FIGS. 2(a) to (1) are diagrams showing the formation process of an eaves pattern according to an embodiment of the present invention, and FIGS. 3(a) to (1)) are diagrams showing the formation of a gate electrode by the method shown in FIG. It is a figure showing a process.

In the figure, the fence is the same as the conventional one, Q4) is the dummy layer provided on the active layer (2), Q4 is the mask layer provided on the side wall of the first layer (Q4), (14a) and (14b) are Table 11iii of this mask layer (b)
These are the hardened layer formed in the ff4 region and the unhardened layer below it. (to) is the resist on which the mask layer α◆ is formed, and α0 is the cured layer (
:L4a) is formed using deep ultraviolet light, and the dummy layer (L4a) is
The opening where 2) was removed, (to) the hardened layer (14)
This is the eaves according to a).

By the way, the pattern mentioned above can be obtained by the following forming process.

First, silicon (Sl) ions, etc., which serve as N-type impurities, are selectively implanted onto the negative main surface of the substrate (1) to form an N-type operating layer (2).
) (Figure 2(a)).

Next, a silicon oxide film (SiOx) is applied to the entire surface.
Oxynitridation, pattern (S10xNy), etc. are vacuum evaporated, CVD
After forming a film to a predetermined thickness by a method or the like, a resist (not shown) is applied and patterned by a phosphorography process to selectively remove unnecessary portions. 2) A dummy layer having a desired rectangular cross-sectional shape with good dimensional accuracy is formed on top (FIG. 82(b)).

Next, for example, a positive type resist Q is spin-coated on the entire surface and deposited to a predetermined thickness so as to cover the dummy layer (2) (Fig. 2 (0)'). The resist (to) is continuously removed so that the gummy layer (to) and the resist (to) have the same main surface, that is, the main surface of the dummy layer (to) is exposed (second Figure (d))
o At this time, the above resist (T) can be removed by light development treatment or reactive etching (hereinafter referred to as R
This is done by an etching process (referred to as process E).

Next, buttering is performed using a phosphorography process, and the resist Q! is applied to the sidewalls of the dummy layer. The resist (g) is selectively removed so that a portion of resist 19 remains with a predetermined width. As a result, a mask layer Q4 provided on the side wall of the dummy layer (to) is obtained (FIG. 2(e)).
.

Next, the entire surface is irradiated with light at a predetermined intensity, for example, with far ultraviolet light uQ having a center wavelength of 300 nm, for a predetermined period of time to harden the mask layer Q4) from the surface to a predetermined thickness. By this light irradiation, the cured layer (14
a) is formed. Below this hardened layer (X4a) is a non-hardened layer (14b) (FIG. 2(f)). In addition,
The irradiation light for forming the cured layer (14a) may be ultraviolet light set under appropriate conditions.

Next, reactive ions that are difficult to be etched for the mask layer α→ and easy to be etched for the dummy layer (to) are selected, and anisotropic etching is performed by RIE or the like, and the dummy layer (to) is etched by anisotropic etching. to) are selectively removed. In addition, on the trace of the dummy layer (to), the mask M
An opening αη surrounded by (14) with good dimensional accuracy and a desired rectangular shape is formed (see Fig. 2(
g)).

Next, wet etching is performed using a hydrogen peroxide mixture or the like to selectively remove the exposed portion of the active layer (2) through the opening αη. Then, when it is etched away to a depth that corresponds to the thickness of the active layer (2) that exhibits a predetermined drain flow characteristic, a recess (b) with an inverted mesa-like cross section is formed (Fig. 2 (→) 0). The recess (b) has a small undercut amount that is approximately the same as the dimension of the opening α9 of the mask layer α4.

Next, the substrate-10 is immersed in an organic acid solution such as isoamyl acetate for a predetermined time, and the uncured layer (14) of the mask layer 04 is immersed in an organic acid solution such as isoamyl acetate.
1))) is selectively dissolved and removed. As a result, the cured layer (14a), which is the remaining portion of the mask layer a4, is completely covered (FIG. 2(1)).

As described above, according to this formation method, the mask layer 0→ is provided on the side wall of the dummy layer (to) processed with high precision, and the mask 111α◆ is uniformly hardened to a desired thickness by irradiating light. A layer (14a) can be formed.

In addition, the opening (171
can be formed into a desired shape, so the above-mentioned operating layer (2)
Not only can high precision be obtained when forming the trench Q (11), but also the mask layer α◆ is not hardened @ (141)
) is removed to form a pattern with good processing accuracy.

Furthermore, by using the above-mentioned pattern, the gate electrode (2) can be fabricated with high processing accuracy as shown in Fig. 3.
can be formed.

That is, first, as shown in FIG. 3(a), a gate metal film α0 made of a Schottky electrode material such as titanium, molybdenum, gold (Ti・MO・Au), aluminum (AI), etc. is deposited on the entire surface using the CvD method at equal pressure. The film is deposited to a predetermined thickness lower than that described above.

Next, the hardened layer (14a) is formed by a lift-off method or the like.
and the gate metal film Ql thereon are removed.

As a result, the above-mentioned excavation (
11) A part of the gate metal film ill remains on the gate, and this becomes the gate electrode, and is formed to have a high dimensional accuracy and a desired cross-sectional shape.

In this way, the hardened F formed to a high fi# degree in the previous step
Since the highly accurate gate electrode (6) is formed using the pattern 5 (14a), excellent characteristics can be obtained and high performance can be achieved.

In addition, in the description of the above embodiment, the gate quadrupole formed using the pattern is the active layer 12.
) The case of a recessed gate structure in which a K recess αp is formed and is provided on it is shown, but it may also be a structure that does not have a recess (b) as shown in Fig. 4. , the dummy layer (up to), the mask layer d→, and the gate metal film αC, etc., can be formed using other relevant steps except for the trenching (1υ) formation step shown in Fig. 2. It is something that is formed.

In addition, although we have shown the case where the gate electrode (6) with Schottky barrier contact is formed by the pattern
The present invention is not limited to this, and can also be applied to other electrodes of ohmic contact, metal wiring, etc., and the same effect as described above can be achieved.

〔Effect of the invention〕

As described above, (1) according to the present invention, a mask layer is formed on the side wall of a dummy layer, the surface area thereof is made into a hardened layer by light irradiation, and the dummy layer and the non-hardened layer of the mask layer are removed. Since a pattern is formed by the above-mentioned hardened layer, a highly accurate pattern can be obtained, and excellent characteristics can be obtained, which has the effect of achieving high performance.

[Brief explanation of the drawing]

FIG. 1 shows an FET of a semiconductor device according to an embodiment of the present invention.
2 (-) to (1) are diagrams showing the formation process of an eaves pattern according to an embodiment of the present invention, and Figures 3 (a) and (b) are m2 diagrams. FIG. 4 is a cross-sectional view showing a gate electrode of another structure formed according to an embodiment of the present invention, and FIG. 5 is a diagram showing a process for forming a gate electrode according to the conventional method.
FIG. 6 is a cross-sectional view showing the structure of the part shown in FIG. In the figure, (1) is a water root, (2) is a gate electrode, and (2) is a water root.
) is a dummy layer, α→ is a mask layer, (14a) is a hardened layer,
(141)) is the uncured layer, 09 is the resist, αQ is the far ultraviolet light, and 0 barrel is the eaves. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A first step of patterning a resist formed by covering a dummy layer provided on a semiconductor substrate, leaving a part of the resist to form a mask layer on the sidewall of the dummy layer, and irradiating light. A second step of forming a hardened layer over a predetermined thickness from the surface of the mask layer.
and a third step of removing the dummy layer and then selectively removing the uncured layer of the mask layer to obtain an eaves of the cured layer.