JPH01122096A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress the increase of charging and discharging currents by the increase of a storage capacity by dividing a bit line into plural small bit lines by switching means and executing a rewriting into memory cells as the small bit lines are charged and discharged successively. CONSTITUTION:The bit line is divided into the two parts of D1--DN and D1''--DN'' by second transfer gates QT1'-Q-TN'. When a transfer gate control signal TG is raised and transfer gates QT1-Q-TN are made into an ON state, the charging and discharging of second bit lines D1''--DN'' are started. Next, after a prescribed delay time, a transfer control signal TG2 is raised and the transfer gates QT1'-Q-TN' are made into the ON state. Thus, the charging and discharging of the bit lines D1--DN are started. When this action is completed, the rewriting into memory cells MC11-MCnN is completed. Thus, the increase of the charging and discharging currents is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a dynamic RAM consisting of one transistor and one cavanter.

[Conventional technology]

Conventionally, the main parts of this type of semiconductor memory have generally had a structure as shown in FIG.

M C+ , to MC, IN indicate l-transistor type memory cells consisting of one MIS type transistor and one capacitor, and are arranged in a matrix.

WL, ~WLn are word lines, WD, ~WDn are circuits that drive word lines WL + ~WLn, SAI ~ SAN
is bit line D1. 0MO3 type sense amplifier, SEP, SEN that amplifies the minute signal read out by "~D82"
are sense amplifier activation signals, YSWI to YS, respectively.
WN is a control signal that selects a bit line pair according to a given address signal and connects to a common data line pair, Ilo, r7?5, 11 is an output circuit, and Dout is an output terminal. FIG. 6 shows a typical operating waveform diagram of the semiconductor memory having the configuration shown in FIG. 2. Bit line DI before the start of operation.

Lπ~D N+51 is connected to the power supply potential Vcc, for example.
It is maintained at an intermediate potential (1/2 Vcc) with respect to the ground potential Vcc. When the row address strobe signal RAS falls, an external address signal (not shown) causes one of the word line drive circuits WD, ~WDn, for example, W
When Di is selected and the word drive signal RA, which is an internal signal generated from RAS, rises, the word line WLi rises, and the N-type MO8) transistors of memory cells MCi 1 to MC1N are ONL, and the voltage is set in each memory cell capacitor. The potential of bit line D+-DN changes by about 200 mV according to the stored charges. - bit line D +
""' The potential of D's is the initial value, that is, 1/2 V
cc remains at the potential, and this difference signal becomes an input signal to the sense amplifiers SA, .about.SA's. Next, when the sense amplifier activation signal SEN rises and SEP falls, the sense amplifiers S A + to S A's are activated, and the minute difference signal input to the sense amplifiers is amplified, and for example, the bit line D1 is set to the ground potential. The bit line “is the power supply potential V
cc (when L information is stored in the memory cell MCi+).Actually, when the word line WLi rises and information is read to the bit line D1, the information in the capacitor of the memory cell MCi+ are destroyed by the exchange of charge with the bit line D1, so the above-mentioned operation of the sense amplifier depends on the bit line D1. It not only amplifies the minute signal on Σ, but also has the function of rewriting (referred to as refreshing) the information of the destroyed cell into the memory cell by reading it to the bit line. Thereafter, as the column address strobe CAS falls, the internal signal column switch activation signal YSW generated by the column address strobe CAS rises in accordance with a column address signal (not shown) externally applied to the address terminal, and as a result, for example, Y
SW, is selected and rises, so that bit line pair D1.
Data on Σ is connected to common data line pair I10. Transferred to m. The transferred data is amplified by the output circuit 11 and output to the outside from the output terminal Dout.

In the above-mentioned conventional technology, as the storage capacity increases, the number of memory cells connected to one bit line increases, so the stray capacitance C11 of the bit line increases, causing various problems. When the sense amplifier is activated as described above, the bit lines D1 to D N Dr -D
N is the power supply potential Vcc or ground potential Vss, respectively.
However, the stray capacitance of the bit line C3
An increase of 1 leads to an increase in the charging/discharging current, resulting in problems such as a floating ground potential, a drop in the power supply potential, generation of noise between bit lines, and an increase in power consumption. In contrast, a configuration as shown in FIG. 3 was considered. The difference with Figure 2 is
Bit lines D+, D+ to DN, DN and sense amplifier S A
+ to SAN as a switch means N-type MO8)
Transfer gate QTI by transistor, Qπ~Q
TN, Q? This is the point where N is provided. This transfer gate Q? The purpose of 1 to Qπ is to reduce the stray capacitance ell of the bit line and the stray capacitance C1□' of the sense nodes DI' to DN''.
The purpose of this invention is to increase the operating speed of the sense amplifier by separating the signals and signals when activating the sense amplifier. A conventional operating waveform diagram for the configuration shown in FIG. 3 is shown in FIG. The control signal TG of transfer gates QTI to QTH is at a high potential during the reset period.
The situation is as follows. The word line WLi is selected and its potential rises in exactly the same manner as the operation explained in FIG. is O
Since it is in the N state, this read information is transmitted as is to the sense node D+'. Transfer gate control signal TG then drops to transfer gate Q,.

becomes OFF state, bit line D+ and sense node D+
' is separated from '. In this state, by raising and lowering the sense amplifier activation signals SEN and SEP, respectively, the sense nodes are set as ', D, - as in the conventional example shown in FIG.
The minute signals are amplified and charged and discharged, one to the power supply potential Vcc and the other to the ground potential. At this time, the stray capacitance t C+ , ' of the sense node D1. The amplification speed is fast because the stray capacitance C+ is small, less than 30% of 1.The sense node is ', D,
- after the amplification of the transfer gate control signal T
Increase the potential of G, transfer) Qt+~Q;
is turned on to start charging and discharging bit lines D1 to core 1. At this stage, the aforementioned rewriting operation to the memory cell is performed. After the charging and discharging of the bit lines D1 to D10; is completed, the transistor Qy++Qπ forming the column switch outputs the control signal when the sense node D+'D+7 is selected, for example, just as in the conventional example shown in FIG. ysw, turns on and data is transferred to the common data line pair/○,
It is transferred to r7?5, passes through the output circuit 11, and is output to the output terminal Do.
Data is output from ut.

[Problem that the invention seeks to solve]

The conventional semiconductor memory described above has the following characteristics: 1. In both the second conventional examples, the stray capacitance C11 or C11 of the bit line tends to increase as the storage capacity increases, and when the bit line is charged and discharged, that is, in the example of FIG. 2, the sense amplifier is activated. Signal SEN.

When SEP rises and falls, respectively, or when the transfer gate control signal TG rises in the example shown in Figure 3, a large charging/discharging current is generated, resulting in a drop in the power supply potential and a rise in the ground potential. For example, if the input time of the column address coincides with the charging/discharging time of the bit line, there is a drawback that the access time is delayed and the input level is incorrectly determined, resulting in malfunction.

[Means for solving problems]

In the semiconductor memory of the present invention, one MIS type transistor and one capacitor constitute a 1-bit memory cell, and a bit line to which a plurality of memory cells are connected is connected to a plurality of switching means. The bit lines are separated into multiple small bit lines by the
It is characterized in that each small bit line starts charging and discharging after a predetermined delay time from the small bit line connected closest to the rewriting means to the small bit lines further away in sequence.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention. Third
The difference from the diagram is that the bit lines are D1 to DN and Dl” to D.
A second transfer agent (QT+') into two parts of N1
This point is separated by the row address strobe R.
When AS falls, the address signal input to the external address bin at that time is taken in, and then one word line drive circuit, for example, WDi, is selected from among the word line drive circuits WDr to WDn based on this address signal.

Thereafter, as the internal signal word line drive signal RA generated by RAS rises, the selected word line WL
The potential of the bit line D1.i increases, and the stored information in the memory cells MCi, . “~DN.

■Appears as a minute signal. At this time, transfer gate control signals TG and TG2 are both in a high potential state, so this bit line pair D+, D+ to DN.

The signal on Σ is applied to the second bit line pair D1″27~DN″
,7 also has the sense node pair ',D,'~De',
The transfer gate control signals TG, TG2 are then lowered, and the bit line pair DzD+~Ds,I)s&second bit line pair D+'',
■−~DN″y and sense node pair, ',D,−~D,'
After separating the D and D, the sense amplifier activation signal SE
By raising and lowering N and SEP, respectively, the sense amplifier S
Activate AI~SAN. The sense nodes D1' to 1 are amplified at high speed because the stray capacitance ftCl1' is relatively small as described above, and for example, one sense node D1
' reaches the power supply potential Vcc and the other sense node D+- reaches the ground potential. After that, the transfer gate control signal TG is raised and the transfer gate (Q Tl -Q TN
By turning on the second bit line D1''~
-2N- starts charging and discharging, and after a certain predetermined delay time, the transfer gate control signal TG2 is raised, and the transfer gates QTI' to Q' are turned on. Discharge is started. When this operation is completed, rewriting to the memory cell is completed. After that, as in the conventional example, the column switch drive signal YSW rises and the column switch transistors QYI and Qπ are activated according to the column address input signal. When it is turned on, data is transferred to the common data line pair I10.If'σ, passed through the output circuit 11, and is output from the output terminal Dout.

The above has described the case where an N-type MO8I-transistor is used as a switching element and a 0MO8-type sense amplifier is used as a sense amplifier. However, the selection of these components, the initial potential of the bit line, the final potential after amplification, etc., are not a problem, and the purpose of this application is to divide the bit line with a large stray capacitance by a switching element. , when rewriting to a memory cell, the bit lines divided in sequence are controlled to start charging and discharging after a predetermined delay time, and the rewriting means is not limited.

[Example 2] FIG. 5 shows an operating waveform diagram of the second embodiment of the present invention.

show. The circuit configuration in this case is the same as in the first embodiment.
It is a diagram. While the transfer gate control signals TG and TG2 remain at a high potential, a word line, for example, WLi, is selected and the potential increases, and the stored information in the memory cells M Ci + to M Ci N is transferred to the bit line pair D1. "~DN, D,, also second bit line pair D1"~■T1 sense node D1'~10,000;7
Then, the transfer gate control signals TG and TG2 fall, and the transfer gate QT
I~Q;,Q,'~QTN'''''' are in the OFF state, and the bit line pair, D, ~DN, D processing second bit line pair D
1'' to 100' and sense nodes DI' to T- are separated, and then the sense amplifiers S A + to SAW are activated by sense amplifier activation signals SEN and SEP, and the minute voltages on the sense nodes DI' to Dpt- are The signal is amplified.Up to this point, everything is exactly the same as in the first embodiment.

The transfer gate control signals TG, TG2 are then kept at a low potential and the selected column switch transistors, e.g. QYII QY, are
I is driven by the rise of the internal signal string switch type dynamic signal YSW generated by CAS and becomes ON state, and the sense node D1'.

The data on p〒7 is a common data line pair 10. m", and the data is output from the output terminal Dout via the output circuit 11. Thereafter, for example, when RAS and CAS rise, that is, when the semiconductor memory enters the reset state, the internal signal YSW first falls, and the column switch transistor Q
y engineering.

Qπ becomes OFF state, transfer gate control signal TG rises, and sense amplifier S A remains activated.
Charging and discharging of the second bit lines D1'' to DN- is started by 1 to SAN, and after a predetermined delay time, the transfer gate control signal TG2 rises, and the transfer gate control signal TG2 is raised.
Since QT,'~QTN'r are in ON state, bit line D
Charging and discharging from 1 to 2 starts, and finally, the bit line pair D
1. "~DNj just the second bit line pair," 10,000T-~
One of the two D5'' has the power supply potential Vcc, and the other has the ground potential.

After that, the word line WLi is lowered. At this point, rewriting (refreshing) to memory cells M Ci + to MC1N is completed. Thereafter, the sense amplifier activation signals SEN and SEP are reset, and the bit lines and sense nodes are reset, thereby completing the reset operation.

In the case of this embodiment, as in the first embodiment, in addition to reducing abnormal peak values of the power supply current and ground current, reducing noise between bit lines, and preventing erroneous determination of the input level of external signals, This has the effect of increasing the access time due to the high-speed operation of the sense amplifier.

〔Effect of the invention〕

As explained above, the present invention divides a bit line with a large stray capacitance into a plurality of small bit lines by a switching means, and charges and discharges the small bit lines sequentially with a predetermined delay time when rewriting to a memory cell. By controlling the bit lines to start, charging and discharging the bit lines with large stray capacitances is not performed all at once, making it easier to reduce noise between the bit lines and reduce abnormal peaks in the power supply current and ground current. This has the effect of reducing erroneous determination of the input level of an external signal and delays in access time due to a drop in power supply potential and a rise in ground potential.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of the present invention, FIGS. 2 and 3 are conventional circuit configuration diagrams, FIG. 4 is an operation waveform diagram for explaining the first embodiment of the present invention, and FIG. The figure shows an operating waveform diagram for explaining the second embodiment of the present invention, and FIGS. 6 and 7 show operating waveform diagrams of a conventional example. WD, ~WDn are word destination drive circuits, WLl~WLn
is the word line, D1~ is the pit line, D+"~T mom-
The divided second bit lines, D1' to ■MA' are sense nodes, M C1t to M CnN are one-transistor type memory cells, Q, 1 to QtN are first transfer gates, Q
TI'~Q;T'''' is the second transfer gate QYI
? QYN is a column switch transistor, SA, ~SAN is a sense amplifier, SEN. SEP is a sense amplifier activation signal, Ilo. T70,000 is a common data line pair, 11 is an output circuit, Dout
indicate the output terminals, respectively. RAS is a row address strobe, CAS is a column address strobe, RA is a word line drive signal, TG and TG2 are transfer gate control signals, and YSW is a column switch drive signal. Agent Patent Attorney Uchihara Sound No. 4 Figure $5 Flash

Claims (1)

[Claims] In a semiconductor memory in which one MIS transistor and one capacitor constitute one bit of memory cell, a bit line to which a plurality of memory cells are connected is separated into a plurality of small bit lines by a plurality of switching means. The present invention is characterized in that during a cell rewriting operation, each small bit line starts charging and discharging after a predetermined delay time from the small bit line connected closest to the rewriting means to the further small bit lines in order. semiconductor memory.