JPH01123204U - - Google Patents
Info
- Publication number
- JPH01123204U JPH01123204U JP1957588U JP1957588U JPH01123204U JP H01123204 U JPH01123204 U JP H01123204U JP 1957588 U JP1957588 U JP 1957588U JP 1957588 U JP1957588 U JP 1957588U JP H01123204 U JPH01123204 U JP H01123204U
- Authority
- JP
- Japan
- Prior art keywords
- pulse train
- process amount
- register
- outputs
- receives
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Feedback Control In General (AREA)
Description
第１図は本考案に係る調節計の一実施例を示す
構成図、第２図及び第５図は従来の調節計を示す
構成図、第３図及び第４図は動作を説明する為の
波形図である。
１…熱電対、２…入力部、４…演算制御部、５
…設定部、６…クロツク発生部、７…リフアレン
スレジスタ、８…出力部、１１…操作端、２０…
アナログ／パルス列変換部、２１…選択部。
Fig. 1 is a block diagram showing an embodiment of the controller according to the present invention, Figs. 2 and 5 are block diagrams showing a conventional controller, and Figs. 3 and 4 are diagrams for explaining the operation. FIG. 1... Thermocouple, 2... Input section, 4... Arithmetic control section, 5
...setting section, 6...clock generating section, 7...reference register, 8...output section, 11...operating end, 20...
Analog/pulse train conversion section, 21... selection section.
Claims (1)
値との偏差に演算処理を施して操作量を出力する
調節計において、 プロセス量をパルス列信号に変換するアナログ
／パルス列変換部と、このパルス列信号とクロツ
クパルスを選択して出力する選択部と、この選択
部の出力が入力されこれらのパルスを積算するレ
ジスタと、このレジスタを読みだしかつ所定の周
期でクリヤする制御部とを有する事を特徴とする
調節計。[Claims for Utility Model Registration] Analog/pulse train conversion converts the process amount into a pulse train signal in a controller that receives a process amount, performs arithmetic processing on the deviation between the process amount and a set value, and outputs a manipulated amount. a selection section that selects and outputs the pulse train signal and clock pulse; a register that receives the output of this selection section and integrates these pulses; and a control section that reads out and clears this register at a predetermined period. A controller characterized by having.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1957588U JPH01123204U (en) | 1988-02-17 | 1988-02-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1957588U JPH01123204U (en) | 1988-02-17 | 1988-02-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123204U true JPH01123204U (en) | 1989-08-22 |
Family
ID=31235208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1957588U Pending JPH01123204U (en) | 1988-02-17 | 1988-02-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123204U (en) |
-
1988
- 1988-02-17 JP JP1957588U patent/JPH01123204U/ja active Pending