JPH0427634U

JPH0427634U -

Info

Publication number: JPH0427634U
Application number: JP6807590U
Authority: JP
Priority date: 1990-06-27
Filing date: 1990-06-27
Publication date: 1992-03-05

Description

[Brief explanation of the drawing]

第１図はこの考案の信号変換装置の一実施例の
ブロツク図、第２図は第１図の動作説明用のタイ
ミングチヤート、第３図は従来の信号変換装置の
ブロツク図である。４ａ，４ｂ……ＣＰＵ、５……プログラマブル
タイマー、６ａ……保持手段、６ｂ……割込発生
手段、７……ＭＰＸ（マルチプレクサ）、９……
Ａ／Ｄコンバータ。 FIG. 1 is a block diagram of an embodiment of the signal conversion device of this invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a block diagram of a conventional signal conversion device. 4a, 4b...CPU, 5...Programmable timer, 6a...Holding means, 6b...Interrupt generation means, 7...MPX (multiplexer), 9...
A/D converter.

Claims

[Claims for utility model registration] A/D conversion of multiple analog signals to generate multiple C
In the signal conversion device for inputting into each PU, a pulse generating means generates a control pulse at predetermined time intervals, and a selection means selectively selects one of the analog signals and outputs the selected analog signal as a selected analog signal. and one A/D converter that A/D converts the selected analog signal and outputs a completion signal when the A/D conversion is completed; comprising a plurality of holding sections holding digital data of the selected analog signal;
holding means for switching the holding section to be held by the control pulse and giving a selection command to the selection means; and a holding means for switching the holding section to be held by the control pulse and giving a selection command to the selection means; A signal conversion device comprising an interrupt generation means for importing digital data of the section.