JPH01123440A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01123440A JPH01123440A JP62281696A JP28169687A JPH01123440A JP H01123440 A JPH01123440 A JP H01123440A JP 62281696 A JP62281696 A JP 62281696A JP 28169687 A JP28169687 A JP 28169687A JP H01123440 A JPH01123440 A JP H01123440A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- collector
- diffusion
- copper
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/221—Structures or relative sizes
- H10W72/224—Bumps having multiple side-by-side cores
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置に関し、特にフリップチップトラ
ンジスタの電極構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an electrode structure of a flip-chip transistor.
第2図は従来のフリップチップNPN)ランジスタの電
極部の断面図であり、図において、1はトランジスタの
N−コレクタ層、2はトランジスタのベース領域を形成
するP拡散層、3はP拡散層2の導体配線であるA1層
、4はN−層1とA1層3とを絶縁するシリコン酸化膜
層、5はトランジスタチップの表面を保護するガラス層
、6はベースのバンプ電極を形成する銅層、7はバンプ
を形成する半田層である。FIG. 2 is a cross-sectional view of the electrode part of a conventional flip-chip NPN) transistor. In the figure, 1 is the N-collector layer of the transistor, 2 is the P diffusion layer forming the base region of the transistor, and 3 is the P diffusion layer. 2 is the A1 layer which is the conductor wiring, 4 is the silicon oxide film layer that insulates the N-layer 1 and A1 layer 3, 5 is the glass layer that protects the surface of the transistor chip, and 6 is the copper that forms the bump electrode of the base. Layer 7 is a solder layer forming bumps.
次に電極部につき詳細に説明する。Next, the electrode portion will be explained in detail.
上記A!1ii3はP拡散層2とオーミックが保たれる
よう形成され、また上記鋼1i16は該A1層3と電気
的に導通があるように形成されており、当然鋼N6も上
記半田層7も電気的に良導体である。Above A! 1ii3 is formed so as to maintain ohmic contact with the P diffusion layer 2, and the steel 1i16 is formed so as to be electrically conductive with the A1 layer 3. Naturally, the steel N6 and the solder layer 7 are also electrically conductive. It is a good conductor.
すなわちP拡散N2と銅層6及び半田層7とは電気的に
接続され、銅N6.半田層7はP拡散712であるベー
ス領域の電極となっている。また銅層6とN−コレクタ
層1との間にはシリコン酸化膜N4が形成されており、
ベース領域の配線であるAl153とN−コレクタFi
llとは電気的に絶縁されている。That is, the P diffusion N2 is electrically connected to the copper layer 6 and the solder layer 7, and the copper N6. The solder layer 7 serves as an electrode for the base region, which is the P diffusion 712. Further, a silicon oxide film N4 is formed between the copper layer 6 and the N-collector layer 1.
Al153 wiring in the base area and N-collector Fi
It is electrically insulated from ll.
ところが、このような電極構造では以下のような問題点
があった。However, such an electrode structure has the following problems.
第3図は第2図の銅層6周辺の拡大図で、図中8はシリ
コン酸化膜層4にできたピンホールであリ、従来の半導
体装置ではこのピンホール8がかりに下部のN−層1ま
で達しない場合、初期的には絶縁が保たれるが、銅層6
からの外部応力によってピンホール8が進行し、コレク
タであるN−1とベースの電極であるA1層3とが電気
的に繋がってしまうことがあり、信頼性が低いといった
問題があった。FIG. 3 is an enlarged view of the vicinity of the copper layer 6 in FIG. If it does not reach layer 1, insulation is maintained initially, but copper layer 6
The pinhole 8 may develop due to external stress from the pinhole 8, and the collector N-1 and the base electrode A1 layer 3 may become electrically connected, resulting in a problem of low reliability.
この発明は上記のような問題点を解消するためになされ
たもので、シリコン酸化膜層のピンホールが銅層からの
応力によって低濃度コレクタ層に達しても、該低濃度コ
レクタ層とベースの電極であるA1層とを電気的に絶縁
した状態に保つことができ、信頼性゛の向上を図ること
ができる電極構造をもつ半導体装置を得ることを目的と
する。This invention was made to solve the above problems, and even if a pinhole in the silicon oxide film layer reaches the low concentration collector layer due to stress from the copper layer, the connection between the low concentration collector layer and the base An object of the present invention is to obtain a semiconductor device having an electrode structure that can maintain an electrically insulated state from the A1 layer, which is an electrode, and can improve reliability.
この発明にかかる半導体装置はバンプ電極用銅層直下の
低濃度コレクタ層内に該コレクタ層とは逆の導電型の半
導体拡散層を設けたものである。The semiconductor device according to the present invention includes a semiconductor diffusion layer of a conductivity type opposite to that of the collector layer in the low concentration collector layer immediately below the bump electrode copper layer.
この発明においては、バンプ電極用銅層直下の低濃度コ
レクタ層内に該コレクタ層とは逆の導電型の半導体拡散
層を設けたから、該コレクタ層と上記バンブ電極の配線
層との間の絶縁膜のピンホールが上層からの応力により
該コレクタ層に達しても、該コレクタ層と上記半導体拡
散層との間のP−N接合によって該コレクタ層と棲上記
配線層とを絶縁状態に保つことができる。In this invention, since a semiconductor diffusion layer of a conductivity type opposite to that of the collector layer is provided in the low concentration collector layer directly under the bump electrode copper layer, there is no insulation between the collector layer and the wiring layer of the bump electrode. Even if a pinhole in the film reaches the collector layer due to stress from an upper layer, the collector layer and the wiring layer above the semiconductor diffusion layer are kept in an insulated state by a P-N junction between the collector layer and the semiconductor diffusion layer. Can be done.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例によるフリップチップ型トラ
ンジスタの電極構造を示し、図中第2図と同一符号は同
一のものを示し、9は銅層6の直下のN−コレクタ層内
に形成されたP拡散層である。FIG. 1 shows the electrode structure of a flip-chip transistor according to an embodiment of the present invention, in which the same reference numerals as in FIG. This is the formed P diffusion layer.
次に作用効果について説明する。Next, the effects will be explained.
このようなフリップチップ型トランジスタでは、上記銅
N6直下のシリコン酸化膜層4に存在するピンホール8
が銅層6からの応力によってP拡散N9に達しAlN3
とP拡散層9とが電気的に導通状態になった場合、ベー
スであるP拡散層2とP拡散層9とが同電位となって、
活性領域ではN−コレクタ層1の電位の方がP拡散層9
の電位より高くなり、つまりP−N接合が逆バイアスさ
れることとなり、その結果A1層3とコレクタN1とを
電気的に絶縁することができる。In such a flip-chip transistor, the pinhole 8 existing in the silicon oxide film layer 4 directly under the copper N6
reaches the P diffusion N9 due to the stress from the copper layer 6, AlN3
When the P diffusion layer 9 and P diffusion layer 9 become electrically conductive, the P diffusion layer 2 as the base and the P diffusion layer 9 become at the same potential,
In the active region, the potential of the N- collector layer 1 is higher than that of the P diffusion layer 9.
In other words, the PN junction is reverse biased, and as a result, the A1 layer 3 and the collector N1 can be electrically insulated.
また、飽和領域ではN−コレクタN1の電位がP拡散層
9の電位より下がるが、ベースであるP拡散層2の電位
がN−コレクタN1の電位より低いので、ベース領域の
面積が拡大したくらいの影響しかなく、特性には影響な
い。Also, in the saturation region, the potential of the N-collector N1 is lower than the potential of the P-diffusion layer 9, but since the potential of the P-diffusion layer 2, which is the base, is lower than the potential of the N-collector N1, the area of the base region is expanded. It has no effect on the characteristics.
なお、上記実施例ではNPN l−ランジスタのベース
部のバンブ電極について示したが、これはエミッタ電極
部でもよ(、同様の効果が得られることは言うまでもな
い。またトランジスタはPNP型のものでもよく、この
場合はP−コレクタ層内の銅層直下部にN拡散層を設け
れば上記実施例と同様の効果が得られる。In the above embodiment, the bump electrode at the base of the NPN l-transistor was shown, but this could also be the emitter electrode (it goes without saying that the same effect can be obtained.Also, the transistor may be of the PNP type. In this case, if an N diffusion layer is provided directly under the copper layer in the P-collector layer, the same effect as in the above embodiment can be obtained.
以上のようにこの発明にかかる半導体装置の電極構造に
よれば、バンブ電極を形成するw4層直下の低濃度コレ
クタ層内に核層とは逆の導電型の半導体拡散層を設けた
ので、該低濃度コレクタ層と銅層間のシリコン酸化膜層
のピンホールが銅層からの応力によってその下側の層に
達しても、該低濃度コレクタ層と上記バンブ電極とを電
気的に絶縁した状態に保つことができ、これにより信頼
性、の向上を図ることができる。As described above, according to the electrode structure of the semiconductor device according to the present invention, the semiconductor diffusion layer of the conductivity type opposite to that of the core layer is provided in the low concentration collector layer immediately below the W4 layer forming the bump electrode. Even if a pinhole in the silicon oxide film layer between the low concentration collector layer and the copper layer reaches the layer below it due to stress from the copper layer, the low concentration collector layer and the bump electrode are electrically insulated. As a result, reliability can be improved.
第1図はこの発明の一実施例による半導体装置の電極構
造を示す断面図、第2図は従来のフリップチップトラン
ジスタの電極構造を示す断面図、第3図は従来のトラン
ジスタの電極構造における問題点を説明するための断面
図である。
1・・・N−コレクタ層、3・・・A1層、4・・・シ
リコン酸化膜層、6・・・銅層、9・・・P拡散層。
なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a cross-sectional view showing the electrode structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the electrode structure of a conventional flip-chip transistor, and FIG. 3 is a problem with the electrode structure of a conventional transistor. FIG. 3 is a cross-sectional view for explaining the points. 1... N-collector layer, 3... A1 layer, 4... silicon oxide film layer, 6... copper layer, 9... P diffusion layer. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
を有する半導体装置において、 上記半導体層のバンプ電極直下の領域に該半導体層とは
逆の導電型の半導体拡散層を設けたことを特徴とする半
導体装置。[Claims] 1) In a semiconductor device having a bump electrode formed on a semiconductor layer via an insulating film, a semiconductor of a conductivity type opposite to that of the semiconductor layer is diffused in a region directly under the bump electrode of the semiconductor layer. A semiconductor device characterized by having a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62281696A JPH01123440A (en) | 1987-11-07 | 1987-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62281696A JPH01123440A (en) | 1987-11-07 | 1987-11-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123440A true JPH01123440A (en) | 1989-05-16 |
Family
ID=17642707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62281696A Pending JPH01123440A (en) | 1987-11-07 | 1987-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123440A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218464A (en) * | 2007-02-28 | 2008-09-18 | Murata Mfg Co Ltd | Semiconductor device |
| US8334594B2 (en) | 2009-10-14 | 2012-12-18 | Advanced Semiconductor Engineering, Inc. | Chip having a metal pillar structure |
| US8552553B2 (en) | 2009-10-14 | 2013-10-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
| US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
| US8698307B2 (en) | 2010-09-27 | 2014-04-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with integrated metal pillars and manufacturing methods thereof |
| US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5580316A (en) * | 1978-12-13 | 1980-06-17 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS5994851A (en) * | 1982-11-24 | 1984-05-31 | Fuji Electric Corp Res & Dev Ltd | Manufacture of semiconductor integrated circuit |
| JPS59181666A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-11-07 JP JP62281696A patent/JPH01123440A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5580316A (en) * | 1978-12-13 | 1980-06-17 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS5994851A (en) * | 1982-11-24 | 1984-05-31 | Fuji Electric Corp Res & Dev Ltd | Manufacture of semiconductor integrated circuit |
| JPS59181666A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218464A (en) * | 2007-02-28 | 2008-09-18 | Murata Mfg Co Ltd | Semiconductor device |
| US8334594B2 (en) | 2009-10-14 | 2012-12-18 | Advanced Semiconductor Engineering, Inc. | Chip having a metal pillar structure |
| US8552553B2 (en) | 2009-10-14 | 2013-10-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
| US8698307B2 (en) | 2010-09-27 | 2014-04-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with integrated metal pillars and manufacturing methods thereof |
| US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
| US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
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