JPH02205355A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To scale down a region to be ensured for an electrostatic protective element by connecting a diode and a bonding pad in the peripheral section of the bonding pad. CONSTITUTION:A bonding pad 14 is connected to a region 7 of a first conductive type through an opening formed to the peripheral section of the bonding pad 14 in an insulating film 11. A buried layer 2 of a second conductive type is connected to a conductive layer 10 near the bonding pad 14. Consequently, a protective element A and the bonding pad 14 are connected directly in the lower section of the bonding pad 14. Accordingly, the degrees of other wirings near the bonding pad 14 are increased, thus ensuring the storage region of the electrostatic protective element A, then securing the degrees of freedom of other wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including an electrostatic protection element connected to an input/output bonding pad.

[Prior Art] In order to protect a semiconductor integrated circuit device (hereinafter abbreviated as IC) from static electricity applied from the outside, various electrostatic protection elements are connected between input or output terminals and the highest potential (VCC> and/or Or it is inserted between the lowest potential (VER).

This protection element is most commonly a diode using a PN junction, and this diode is inserted so that it is reverse biased during actual operation of the IC.

FIG. 4 shows a plan view of a typical conventional electrostatic protection element for a bipolar IC. As shown in the figure, in the conventional example, the electrostatic protection element forming region 41 is located at a different position from the bonding pad 44. The N-type region 42 of the first diode is connected to the highest potential VCC, and the second
The P-type region 45a of the diode is connected to the lowest potential EE.

The P-type region 45 of the first diode and the N-type region 42a of the second diode were connected to a bonding pad 44 for input or output signals.

[Problems to be Solved by the Invention] In the conventional arrangement of the electrostatic protection element described above, the electrostatic protection element is not laid out in a location different from the bonding pad. It was necessary to secure the necessary area on the IC. The actual area of the electrostatic protection element is approximately 100 to 150μ.
In particular, small chip size I
When accommodating a large number of electrostatic protection elements in C, there is a problem in that it is difficult to secure a housing area for the electrostatic protection elements. In addition, two or three wires are connected to the electrostatic protection element, and in the conventional example, space for these wires had to be secured, so the degree of freedom for other wires was reduced accordingly. It was a sacrifice.

[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention includes a second conductive type buried layer formed on a first conductive type semiconductor substrate, and a second conductive type buried layer formed on the second conductive type buried layer. a first conductivity type region;
An insulating film formed on a conductive type region, and a bonding pad disposed directly above the second conductive type buried layer and the first conductive type region with the insulating film interposed therebetween, The bonding pad is connected to the first conductivity type region through an opening formed in the peripheral portion of the bonding pad in the insulating film, and the second conductivity type buried layer is connected to the conductive layer in the vicinity of the bonding pad. is connected to.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention. In the figure, an N-type buried layer 2 is diffused on a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is formed thereon. In this N-type epitaxial layer 3, a P-type region 5 formed by thermal diffusion from polysilicon 4 is provided, and each long region is separated from the others by a LOCOS oxide film 6. The peripheral part of the P type region 5 has a P
A P type region contact region 7 formed by diffusing type impurities is provided. The N-type buried layer 2 is made of N-type semiconductor which has become an N-type semiconductor due to the N-type impurity diffused from the contact hole.
It is connected to the mold buried layer extraction region 8.

The P-type region contact region 7 includes the first layer aluminum 13
and is connected to the second layer aluminum 9 via a through hole formed in the insulating film 11. A portion of the second aluminum layer 9 that is not covered with the cover film 12 serves as a bonding pad 14 . The N-type buried layer 2 is
It is connected to the first layer aluminum 10 via the N-type buried layer extraction region 8 .

With this structure, the bonding pad 14 can accommodate an electrostatic protection diode of approximately the same size directly below it. Since the contact between the P-type region contact region 7 and the first layer aluminum 13 and the contact between the first layer aluminum 13 and the second layer aluminum 9 are made around the bonding pad, the bonding area is It's flat. Further, directly under the bonding pad 14, a relatively thick insulating film 11 is formed between the polysilicon 4 and the P wall region 5.
Since the bonding pads are insulated from each other, the bonding pads do not have large parasitic capacitance.

FIG. 2 is a plan view of FIG. 1 viewed from above.

As shown in the figure, the first layer aluminum 13
The bonding pad 14 has a square frame shape.
located around the periphery of the 12a is the edge of the opening formed in the cover film 12, and inside this edge 12a, the first layer aluminum 10 and the second layer aluminum 9 are exposed, and the first layer aluminum 10 is exposed. The exposed portion of the second layer aluminum 9 is used as the bonding pad 14 as described above.

FIG. 3 is a circuit diagram showing how the electrostatic protection element according to this embodiment is used. In the figure, A is the electrostatic protection element according to this embodiment, and B is the circuit to be protected.

According to this embodiment, since the protection element shown by A is approximately the same size as the bonding pad and is formed directly below it, there is no need to secure a special place for the element, and the element is simply placed. It is only necessary to secure a place for connection (the place indicated by the first layer aluminum 10).

FIG. 4 is a sectional view showing another embodiment of the present invention. In this embodiment, a protection element (hereinafter referred to as a second diode) having a structure similar to that of the first diode is arranged near the protection element in the previous embodiment (hereinafter referred to as a first diode). In this embodiment, the first layer aluminum 13b connected to the P-type head contact region 7 of the first diode is extended to the second diode side,
Therefore, it is connected to the Nfi buried layer 2a of the second diode via the N type buried layer extraction region 8a. Also,
The P-type head region 5a of the second diode is connected to the second layer aluminum 9a via the P-type head contact region 7a and the first layer aluminum 13a. 2nd layer aluminum 9
Here, a is connected to the wiring connected to the lowest potential VEE.

FIG. 5 is a circuit diagram showing the usage state of the protection element of this embodiment, in which A is the electrostatic protection element of this embodiment,
B is the protected circuit.

In this embodiment, the second diode is formed at a separate location from the bonding pad, while the first diode is located directly below the bonding pad.

Therefore, according to this embodiment, the area required to form the protective element is about half that of the conventional example.

Note that the protection element and the highest potential (VCC) or lowest potential (
VER) The connection to the power source can also be made by the second layer aluminum through the first layer aluminum;
It may also be done directly by layer aluminum.

[Effects of the Invention] As explained above, in the present invention, a diode consisting of an N-type region and a P-type head region is arranged directly under a bonding pad, and the connection between this diode and the bonding pad is made at the periphery of the bonding pad. Therefore, according to the present invention, the area that must be reserved for the electrostatic protection element is significantly reduced, and since the protection element and the bonding pad are directly connected at the bottom, the bonding pad is The degree of freedom for other wiring in the vicinity increases.Furthermore, since the bonding pad is connected to the protection element at its periphery, the flatness of the bonding area of the bonding pad is maintained, resulting in good bonding performance. is ensured.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention.
1 is a plan view, FIG. 3 is a circuit diagram showing how the device of the embodiment shown in FIG. 1 is used, FIG. 4 is a sectional view showing another embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing how the element of the embodiment is used, and FIG. 6 is a plan view showing a conventional example. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2.2a... N-type buried layer, 3... N-type epitaxial layer, 4... Polysilicon, 5.5a... P-type head area, 6...・Locos oxide film, 7.7a...P-type head contact region,
8.8a... N-type buried layer extraction area, 9.9a.
...Second layer aluminum, 10.13.13a, 13
b...First layer aluminum, 11...Insulating film, 1
2... Cover film, 14... Bonding pad, A... Electrostatic protection element, B... Circuit to be protected.

Claims (2)

[Claims] (1) A second conductivity type buried layer formed on a first conductivity type semiconductor substrate, a first conductivity type region formed on the second conductivity type buried layer, and a first conductivity type region formed on the first conductivity type region. In a semiconductor integrated circuit device comprising an insulating film formed, and a bonding pad disposed directly above the second conductivity type buried layer and the first conductivity type region with the insulating film interposed therebetween, the bonding pad is The insulating film is connected to the first conductivity type region through an opening formed around the bonding pad, and the second conductivity type buried layer is connected to the conductive layer in the vicinity of the bonding pad. A semiconductor integrated circuit device characterized by: (2) a second conductivity type buried layer formed on a first conductivity type semiconductor substrate, a first conductivity type region formed on the second conductivity type buried layer, and a first conductivity type region formed on the first conductivity type region; an insulating film formed, a bonding pad disposed directly above the second conductivity type buried layer and the first conductivity type region with the insulating film interposed therebetween, and a diode element provided near the bonding pad. In the semiconductor integrated circuit device, the bonding pad is connected to the first conductivity type region through an opening formed in the peripheral portion of the bonding pad of the insulating film, and the second conductivity type region of the diode is connected to the first conductivity type region. is connected to the bonding pad, and the first conductivity type region of the diode and the second conductivity type buried layer are each connected to a conductive layer in the vicinity of the bonding pad.