JPH01125032A - Input/output signal monitoring circuit - Google Patents

Abstract

PURPOSE:To inhibit a fact that an error generated in a transmission line is detected as a bit collation error by detecting whether an AIS signal exists in a monitoring circuit input signal or not and inhibiting the generation of an error alarm caused by a bit collation in the course of detecting the AIS signal. CONSTITUTION:An input signal 8 is code-converted by an encoding circuit 1, and thereafter, passes through a transmission line 2 and is sent to a decoding circuit 3. In the decoding circuit 3, the inverse conversion of the encoding circuit 1 is executed, and an output signal 9 is obtained. The signal passing through the transmission line 2 is inputted to the same decoding circuit 4, as well, as the decoding circuit 3. To a bit collating circuit 5, the output signals of the decoding circuit 3 and the decoding circuit 4 are inputted, and the error monitoring of bit-by-bit is executed. The output signal of the decoding circuit 4 is supplied to an AIS signal detecting circuit 6, as well, and when an AIS signal is transmitted from the encoding circuit 1, it is detected and an AIS signals detecting signal is transmitted to an error alarm generation inhibiting circuit 7. When the AIS signal detecting signal is received, the error alarm generation inhibiting circuit 7 executes an obstruction so that an error alarm generated by the bit collating circuit 5 is not generated to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output signal monitoring circuit for a terminal relay device, which is one of the most important aspects of the digital communication system.

[Conventional technology]

A conventional input/output signal monitoring circuit will be explained using FIG. 2.

FIG. 2 is an example in which an input/output signal monitoring circuit is used as a decoding circuit. The input signal 8 undergoes code conversion by the encoding circuit 1. The code-converted signal passes through the transmission line 2 to the decoding circuit 3.
The signal is input to the encoder circuit 1, where it undergoes inverse transformation to obtain an output signal 9.

The signal passing through the transmission line 2 is also input to a decoding circuit 4 having the same function as the decoding circuit 3, and its output signal is sent to a bit verification circuit 5. The output signal of the decoding circuit 3 is also input to the bit matching circuit 5. If there is a time difference between the output signals of the two decoding circuits, the bit matching circuit 5 cannot detect the error 41) t-, so after eliminating the difference in delay time and achieving phase synchronization between the bits, pie
Error monitoring is performed by comparing bits.

Bit-pi-bit error monitoring is also used to detect delay time differences. When the input signal to the bit matching circuit 5 is random, and the delay amounts of the two signals do not match, the error rate becomes approximately A as a result of bit-pi-bit monitoring. On the other hand, when the delay amounts match, the error rate becomes 0 or a value sufficiently smaller than %, so it is determined that the phase synchronization between the bits has been achieved and the delay time is not shifted any further. Here, when the error rate is 10-3 or less, it is assumed that the delay time difference has disappeared, and when the error rate is 10-6 or more, it is assumed that there was an error in the decoding circuit, and an alarm is issued.
It is assumed that t occurs.

[Problem that the invention seeks to solve]

In the conventional input/output signal monitoring circuit described above, the input signal to the bit matching circuit 50 is not random (in the case of an AIS signal, the delay amount of the two signals does not match, even if it is a bit-pi-bit monitoring circuit). As a result, the error rate becomes 0 and false synchronization occurs.At this time.

If an error of 10-5 occurs in the transmission path 2, the error rate will be 10-3 or less even if the delay amounts between the input signals of the bit matching circuit 50 do not match, so it is determined that synchronization is achieved. do. However, as a result of bit matching, an error of about IO is detected, so there is a drawback that an alarm 11 is issued.

[Means for solving problems]

The input/output signal monitoring circuit of the present invention detects that an AIS signal is input as a signal for error monitoring.
The present invention is characterized in that it includes a signal detection circuit and a circuit that prohibits the issuance of an error alarm when there is an output from the AIS signal detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention).

The same parts as in FIG. 2 are given the same numbers. input signal 8
after undergoing code conversion by the encoding circuit IK.

The signal is sent to the decoding circuit 3 via the transmission line 2t. The decoding circuit 3 performs the inverse transformation of the encoding circuit 1 to obtain an output signal 9. The signal passing through the transmission path 2 is also input to the same decoding circuit 4 as the decoding circuit 3. The output signals of the decoding circuit 3 and the decoding circuit 4 are inputted to the bit matching circuit 5, where bit-pi-bit error monitoring is performed. The output signal of the decoding circuit 4 is also supplied to the AIS signal detection circuit 6, and when the AIS signal is transmitted from the encoding circuit 1 to j9, it is detected and the AIS signal detection signal 1 is sent to the error alarm generation prohibition circuit 7. Send. A1. Upon receiving the S signal detection signal, the error alarm issuance prohibition circuit 7 prevents the error alarm issued by the bit comparison circuit 5 from being issued to the outside.

Although the above embodiment has been explained by applying it to a decoding circuit, 2
It is clear that the scope of the invention is not limited to decoding circuits.

〔Effect of the invention〕

As explained above, one aspect of the present invention is that the input signal of the pit verification circuit is caused by the input signal of the monitoring circuit to cause erroneous synchronization due to the AIS signal, which is further detected as an erroneous bt pit verification error occurring in the transmission path. This has the effect of prohibiting the issuance of such information.

[Brief explanation of the drawing]

FIG. 1 is a 20-step diagram of the input/output monitoring circuit of the present invention. FIG. 2 is a block diagram of a conventional input/output monitoring circuit. 8: Input signal, 9: Output signal, 10, 11: Pit matching error alarm.

Claims (1)

[Claims] 1. Error monitoring that occurs between the input and output of the conversion circuit in the terminal relay device is performed between the conversion circuit output signal and the output signal when the same input signal is applied to a circuit that has the same function as the conversion circuit. In an input/output signal monitoring circuit that performs bit-by-bit comparison, an AIS signal detection circuit detects that an AIS signal is input as a signal for error monitoring, and input/output is performed using the output signal of the AIS signal detection circuit. An input/output signal monitoring circuit comprising a circuit for inhibiting error detection output from the signal monitoring circuit.