JPH01126185A - Speed controller - Google Patents

Abstract

PURPOSE:To stably work a speed controller up to a high frequency range, by estimating the speed error data of output to be generated before the output of the speed error data is generated by an intermediate point error estimating means. CONSTITUTION:By a counter 9, intervals in every period of speed signal are counted, and the output of an average speed counted-value in a counting block is generated. From a speed error arithmetic block 10, the output of a speed error data obtained from the average speed measured-value is generated. By an intermediate point error estimating block 20, through an average measured- value at each counting time point and a measured value before the time point, the speed error data of output to be generated before the output of a following speed error data is generated is estimated, and the output of its data is generated. Based on the output data of the speed error arithmetic block 10 and the output data of the intermediate point error estimating block 20, a motor 1 is driven.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a speed control device that measures the period of a speed signal of a controlled object such as a rotating body and drives the controlled object based on error data from a reference value. It is.

BACKGROUND OF THE INVENTION FIG. 6 shows a typical functional block diagram of a rotational speed control system for a capstan motor in a home video tape decoder. In FIG. 6, the frequency generator 2 connected to the capstan motor 1 outputs an AC signal as shown in FIG. 7A, but this AC signal depends on the rotation speed of the capstan motor 1. It has a repetition period, and the FC signal amplifier 3
The waveform is amplified and shaped into a square wave as shown in the figure below.

Further, in the multiplier circuit 4, the signal waveform shown in FIG. 7C is generated from the signal waveform shown in FIG. 7B, and sent to the speed error detector 5. On the other hand, the speed error detector 5 digitally measures the period from the leading edge of the signal waveform shown in FIG. 7C to the next leading edge using a counter, etc., and outputs error data from the fixed reference value. Ru.

This error data is subjected to gain compensation in the frequency domain by the digital filter 6 and then supplied to the D-A converter 7, and the output of the D-A converter 7 is used in the motor drive circuit for driving the capstan motor 1. 8.

Therefore, the blocks shown in FIG. 6 constitute a closed loop speed control system for rotating the capstan motor 1 at a constant speed.
is used to improve the responsiveness of speed control systems.

That is, the rotational speed of the capstan motor is as shown in Fig. 7C.
Each time the leading edge of the signal waveform arrives, it is measured as the average value of the speed change from the time the previous leading edge arrived (generally called a moving average).
However, if the multiplier circuit 4 is not used, the measurement will be performed between the leading edges of the signal waveform shown in FIG. is the output frequency of frequency generator 2 (
Hereinafter, it will be abbreviated as FG frequency. ) can be made higher, but
There were limitations due to problems with mechanical processing accuracy. Therefore, a method of electrically multiplying the FG frequency is often used, and
The edge multiplication method shown in the figure is a typical example.

Problems to be Solved by the Invention Incidentally, the maximum operating frequency of the control JTj system in such a speed control device is regulated by the FC frequency, and this is illustrated in the block diagram of the control system shown in FIG. This will be explained with reference to. First, in Fig. 8, Kt (g-e1m/A), which represents the torque constant of the motor, and the inertia and viscosity blocks represent the motor transfer function, and J (g-01・5ec-sac/rad) is The moment of inertia, D (g-cm·aec/rad) is viscous resistance, and S is the Laplace operator. The rotational speed of the motor is controlled by a frequency generator (FG) with P teeth per rotation.
) is converted into a speed signal by a counter configured with an input/output sampler, a counter, and a moving average element to measure the interval of each period of this speed signal. The transfer function Gc of the counter section excluding the sampler is expressed by the following equation.

However, 2π Here, F(k (Hz)) is the frequency of the reference clock supplied to the counter, and "l" (sec) is the sampling period.

The reference value is subtracted from the measured value output from the counter,
The error data is supplied to a zero-order holder constituted by an input buffer of a DA converter via a digital filter having a transfer function Of. The transfer function of this zero-order holder is good (as is known, it is given by the following equation.

Also, the number of bits of the D-A converter is n, and the supply voltage is V.
cc, the conversion gain Kx of the DA converter is given by the following equation.

The output of the D-A converter is the transfer conductance gm (A
/V), and its output current is supplied to the motor.

Now, among each block in FIG. 8, the sampling period T
It is the counter and the holder that change the phase characteristics of the transfer function by , and the phase characteristics θC9θh of both with respect to the Ninokura frequency f are as follows from the equations [1 and +31, respectively.

θC-π・f-T ・・・・・・(
5) θh-π・f-T...
・(6) On the other hand, in order for the control system to operate stably, a phase margin of 40 to 60 degrees is required at the frequency where the open loop gain becomes 0, but at that frequency, the inertia and viscosity shown in Figure 8 are Among the transfer functions within the block, the inertia term becomes dominant, and a 90 degree phase delay occurs in this portion. Therefore, if we try to secure a phase margin of 60 degrees, (
The sum of θC and θh given by formula 51, +61 is 30 degrees,
That is, it needs to be smaller than π/6. From this condition, the relationship between the FC frequency Ffg and the highest frequency Fc that can be stably controlled is determined, and the following equation holds true.

Fc Tsu□ 2T 2T In this way, the maximum operating frequency of the control system in the speed control device is regulated by the FC frequency, but the Fc frequency mentioned earlier
The C frequency multiplication method shortens the sampling period T by half by utilizing the leading edge and trailing edge of the speed signal, which effectively reduces the frequency by 6
It has the effect of widening the control band to one-fold the frequency. However, with the conventional technology, there is a limit to improving the control characteristics to this extent, and in order to expand the control band to a higher frequency, it was necessary to increase the FC frequency itself.

Means for Solving the Problems In order to solve the above problems, the speed control device of the present invention outputs speed error data obtained from the average speed measured at each measurement point by the average speed measuring means. and an intermediate point that predicts the speed error data to be output before the next speed error data is output from the average measured value at each measurement point and the previous measured value and outputs that data. The apparatus includes an error prediction means, and a drive means for driving the controlled object based on the output data of the speed error calculation means and the output data of the intermediate point error prediction means.

Function: According to the present invention, with the above-described configuration, it is possible to realize a speed control device that can stably operate up to a higher frequency than ever before.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a speed control device according to an embodiment of the present invention, and blocks that are the same as those in FIG. 6 are designated by the same figure numbers. In the device shown in FIG. 1, a counter 9 counts an external reference clock.
The output data of the speed error calculation block 10 is supplied to the speed error calculation block 10, the output data of the speed error calculation block 10 is supplied to the midpoint error prediction block 20, and the output data from the midpoint error prediction block 20 is supplied to the digital filter 6. ing. Further, the output signal of the multiplier circuit 4 is supplied as a control signal to the counter 9, the speed error calculation block 10, and the midpoint error prediction block 20.

The speed error calculation block 10 includes an adder 11 that adds the count amount of the counter 9 and a reference value when the leading edge of the output signal of the multiplier circuit 4 arrives, and an adder 11 that adds reference value data to the adder 11. a reference value generator 12 for supplying a reference value generator 12; and a first
When the leading edge of the output signal of the multiplier circuit 4 arrives, the midpoint error prediction block 20 is configured with a memory 13, and a second memory 21 that stores the data stored up to that point in the first memory 13. , a predictor 22 predicts the transition of data at that time from the data stored in the first memory 13 and the second memory 21 after the leading edge of the output signal of the multiplier circuit 4 arrives. Incidentally, the sampling clock of the digital filter 6 is supplied from the multiplier circuit 4 and the preamplifier 22. Further, it is assumed that the reference value generator 12 outputs data with a negative sign in order to cause the adder 11 to perform subtraction.

The operation of the speed control device configured as described above will be explained based on the block diagram of FIG. 1, the flowchart of FIG. 2, and the signal waveform diagram of FIG. 3. Note that FIG. 2 is a flowchart showing the operation of the midpoint error prediction block 20, and in this flowchart, registers not shown in the block diagram of FIG. 1 are used;
Speed error calculation block 10 using a microprocessor
It is assumed that the operation of the midpoint error prediction block 20 is performed, and the first memory 13 and the second memory 2
1 and the third memory used in the flowcharts can both use the data memory in the microprocessor, and various arithmetic operations such as addition and subtraction can also be performed using the arithmetic logic unit ( ALU). In addition, Fig. 3A is an output signal waveform diagram of frequency power generation a2, and Fig. 3B
is an output signal waveform diagram of the multiplier circuit 4. FIG.

At branch 61 in FIG. 2, it is determined whether the leading edge of the speed signal output from the multiplier circuit 4, that is, the signal shown in FIG. , if no new leading edge has arrived, the process moves to branch 66.

A processing block 62 transfers the data stored in the first memory 13 in FIG.
The first memory 13 stores average error data obtained by adding a reference value to the count amount per section output from the first memory 13.

In the processing block 63, the value of the data in the first memory 13 is subtracted from the value of the data stored in the second memory 21, stored in a register, and the value in the register is multiplied by a prediction coefficient value prepared in advance. In order to store the result in the register again, subtract the register value from the value of the data stored in the first memory 13, and temporarily save the result, It is stored in the third memory.

In the processing block 64, the value of the data in the first memory 13 is subtracted from the value of the data stored in the second memory 21, and the result is stored in a register, thereby halving the value in the register.

The processing block 65 subtracts the value of the register from the value of the data stored in the first memory 13 and outputs the result. This output data is supplied to the digital filter 6 in FIG.

The meaning of this series of processing will be explained using FIG. 3. Third
Assuming that the processing in processing blocks 62 to 65 is performed after time t5 in the figure, the processing in processing block 62 causes the first memory 13 to store data at time t3.
The second memory 21 stores data dependent on the average speed error of the capstan motor in the section from time t1 to time t5, and the second memory 21 stores data dependent on the average speed error in the section from time t1 to time t3. Assuming that the instantaneous measurement value of the rotational speed error of the capstan motor during one cycle of the speed signal from t1 to time t5 can be approximated by a straight line, the data stored in the first memo 'J13 is calculated at time t4, i.e. , represents the instantaneous measurement value m1 at the midpoint between time t3 and time t5, and the second memory 21
The data stored in will represent the instantaneous measurement value m2 at time t2. Therefore, time t5 in FIG.
The estimated value RO of the instantaneous measurement value at is determined by executing the following calculation, which is performed in the processing unit 74 and processing block 65.

2-ml RO=m 1-- --- (81) Now, the relationship between times t3, t5, and t6 in FIG. 3 is set as follows.

t 5 - t 3 t 6 = t, 5 + □ ・・
(9) That is, the time from time t5 to time t6 is set to be half the time from time t3 to time t5. Therefore, from time t3 to time t
If the instantaneous error in the rotational speed of the capstan motor changes linearly between t6 and t6, then the instantaneous error R1 at time t6 is calculated by subtracting the second term on the right side of equation (8) from the estimated value RO found by equation (8). All you have to do is subtract it. However, while the estimated value RO of the instantaneous error at time t5 can be estimated based on the measured value of the actual average speed between time t3 and time t5, the instantaneous error at time t6 from time t5 to The prediction of R1 has a high degree of ambiguity because the behavior of the capstan motor from time t5 to time t6 is unknown. In fact, the output of the estimated error RO at time t5 affects the instantaneous rotational speed at time t6, although the degree of influence differs depending on the moment of inertia of the capstan motor, and the actual instantaneous error is shown in Figure 3. It becomes smaller than the size of R1.

Therefore, in the processing block 63, the value obtained by subtracting the data value m1 of the first memory 13 from the data value m2 stored in the second memory 21 is multiplied by a prediction coefficient smaller than 1. The predicted value is derived. This prediction coefficient can be prepared in advance as a fixed value that reflects the moment of inertia of the capstan motor 1. Furthermore, after time t7 in Figure 3 has passed, the average speed error in the section from time t5 to time t7 is measured, so at that point the validity of the prediction coefficient value is evaluated and corrected. You can also do that.

At branch 66 in FIG. 2, it is determined whether or not the second error data output point has arrived. We are making a meeting.

When the second error data output point arrives, a processing block 63 outputs the predicted value of the instantaneous error saved in the third memory, and a processing block 67 causes the digital filter 6 to start sampling. (Sampling clock supply,).

In the flowchart of FIG. 2, the addition of the counted amount and the reference value in the processing block 62 and the storage of the addition result in the first memory are performed by the speed error calculation block 10.
All other processing is performed by the midpoint error prediction block 20.

In this manner, in the speed control device shown in FIG. 1, the instantaneous value of the speed error of the capstan motor 1 constitutes the midpoint error prediction block 20, for example at time t5 and time t6 in FIG. Since the estimated value RO and the predetermined value R1 are output from the predictor 22, the maximum controllable frequency Fc is higher than that of the conventional speed control device.

By the way, in the embodiment shown in FIG. 1, the estimated value RO and the predicted value R1 are output from the midpoint error prediction block 20, but at time t5 in FIG. If the average speed error data m1 is output and the estimated value RO of the instantaneous speed error is output as the predicted value of the average speed error at time t6, the effect of expanding the control band will be reduced, but the prediction processing will be It gets easier. 4 and 5 respectively show a block diagram and a flowchart in this case. As can be seen from FIG. 5, in the speed control device shown in FIG. At time t5, the measured average speed error data ml is output as is, and when time t6 arrives, a predicted value RO of the average speed error is derived and output.

In the speed control devices shown in FIGS. 1 and 4, when the sampling period of the output signal of the multiplier circuit 4 is T, the input data of the digital filter 6 is updated at a period of T/2, and the sampling period of the digital filter is Since the clock period is also T/2, the phase characteristic θh of the zero-order holder configured by the input buffer of the D-A converter is
is given by the following equation.

π · f-T Therefore, the phase delay in this part is half of that of the conventional one, and assuming that the multiplier circuit 4 is used, the relationship between the FC frequency Ffg and the maximum frequency F'c that can be stably controlled is as follows. Become.

4.5 Effects of the Invention As is clear from the above explanation, the speed control device of the present invention measures the interval for each period of a speed signal whose period depends on the speed of a controlled object, such as a capstan motor. An average speed measuring means (in the embodiment, the average speed measuring means is realized by the counter 9, but it can also be realized by a combination of a microprocessor program and a data memory, etc.) and outputs it as an average measured value in the measurement section. ), a speed error calculation means (speed error calculation profile 10) that outputs speed error data obtained from the measured value of the average speed, and the average measured value at each measurement point and previous measured values. intermediate point error prediction means (halfway point error prediction block 20) that predicts speed error data to be output before outputting the next speed error data and outputs that data; and an output of the speed error calculation means. Driving means (
Since the motor drive circuit 8) is provided, it is possible to realize a speed control device that can stably operate up to a higher frequency than ever before, which has great effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a speed control device showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the device in FIG. 1, and FIG. 3 is a signal waveform diagram of the main parts of FIG. 1. FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a flowchart explaining the operation of the device shown in FIG. 4, FIG. 6 is a block diagram showing a conventional example, and FIG. Figure 8 is a block diagram showing the transfer function of the control system.
... Capstan motor, 8 ... Motor drive device, 9 ... Counter, 1o ... Speed error calculation block, 20 ... Midpoint error prediction block. Name of agent: Patent attorney Toshio Nakao
sect

Claims (1)

[Claims] An average speed measuring means for measuring an interval for each period of a speed signal having a period dependent on the speed of the controlled object and outputting it as an average measured value in the measurement interval, and speed error data obtained from the measured value of the average speed. An intermediate device that predicts the speed error data that should be output before the next speed error data is output based on the average measured value at each measurement point and the previous measured value, and outputs that data. A speed control device comprising: point error prediction means; and drive means for driving the controlled object based on output data of the speed error calculation means and output data of the intermediate point error prediction means.