JPH01126741U - - Google Patents

Info

Publication number
JPH01126741U
JPH01126741U JP2122288U JP2122288U JPH01126741U JP H01126741 U JPH01126741 U JP H01126741U JP 2122288 U JP2122288 U JP 2122288U JP 2122288 U JP2122288 U JP 2122288U JP H01126741 U JPH01126741 U JP H01126741U
Authority
JP
Japan
Prior art keywords
pcm
signal output
signals
ram
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2122288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2122288U priority Critical patent/JPH01126741U/ja
Publication of JPH01126741U publication Critical patent/JPH01126741U/ja
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示すブロツク図であ
る。 1:信号入力変換部、2:マルチプレクサ、3
:A/Dコンバータ、4:RAM、5,6,7:
PCM信号出力部、8:ラツチ回路、9:パラレ
ルシリアルコンバータ、10:バスライン、11
:PROM。
FIG. 1 is a block diagram showing an embodiment of the present invention. 1: Signal input conversion section, 2: Multiplexer, 3
: A/D converter, 4: RAM, 5, 6, 7:
PCM signal output section, 8: latch circuit, 9: parallel serial converter, 10: bus line, 11
:PROM.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のチヤンネルのアナログ信号を時分割多重
化するPCMエンコーダにおいて、信号入力変換
部からのパラレル出力信号を一時記憶するRAM
と、ラツチとパラレルシリアルコンバータとから
なる複数のPCM信号出力部とを備え、上記RA
Mの出力と上記PCM信号出力部の入力とをバス
ライン形式で接続し、かつ、上記RAMおよびP
CM信号出力部をPROMにより制御してPCM
フレームフオーマツトの異なる複数のPCM信号
を出力することを特徴としたPCMエンコーダ。
In a PCM encoder that time-division multiplexes analog signals of multiple channels, a RAM that temporarily stores parallel output signals from a signal input converter.
and a plurality of PCM signal output sections each consisting of a latch and a parallel-to-serial converter.
The output of M and the input of the PCM signal output section are connected in a bus line format, and the RAM and P
PCM by controlling the CM signal output section with PROM
A PCM encoder characterized by outputting a plurality of PCM signals with different frame formats.
JP2122288U 1988-02-22 1988-02-22 Pending JPH01126741U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2122288U JPH01126741U (en) 1988-02-22 1988-02-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2122288U JPH01126741U (en) 1988-02-22 1988-02-22

Publications (1)

Publication Number Publication Date
JPH01126741U true JPH01126741U (en) 1989-08-30

Family

ID=31238264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2122288U Pending JPH01126741U (en) 1988-02-22 1988-02-22

Country Status (1)

Country Link
JP (1) JPH01126741U (en)

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