JPH01126833A - Circulating type noise reducer circuit - Google Patents

Abstract

PURPOSE:To improve the noise reduction effect without generating the blurring of a signal by devising a circuit such that a signal (Y signal) circulated with one frame and a signal (C signal) circulated with 2 frames are set respectively with an optimum multiplication coefficient. CONSTITUTION:A signal is given to a Y filter 11 to extract only a noise component and to pass the Y signal only therethrough to eliminate the C signal component and a multiplication coefficient K1 optimum to the Y signal band is multiplied with the output by a 1st multiplier 13, then the output is added to the input signal by an adder 15 to reduce the noise component. In order to the Y signal component, a C filter 12 to pass only the C signal is given to the output of a 2nd subtractor 10 to extract the noise component of the C signal and a multiplication coefficient K2 optimum to the C signal band by the 2nd multiplier 14 to the output, then the output of the 2nd multiplier 14 is added to the input signal by the adder 15 to reduce the noise component. Thus, the multiplication coefficients K1, K2 optimum to the band of the C, Y signals are set independently in this way, then no blurring takes place to both the C, Y signals and the noise reduction effect is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a cyclic noise reducer circuit, and particularly relates to a cyclic noise reducer circuit that reduces noise contained in signals having different correlations (for example, a luminance signal and a carrier color signal of a video signal, etc.). The present invention relates to a circuit that can effectively reduce

(Prior Art) FIG. 2 is a diagram showing a basic circuit of a cyclic noise reducer. This utilizes the correlation of images in the time axis direction, and since noise has no correlation, it has a noise reduction effect in the still image portion.

An input signal is input to input terminal 1, an output signal is taken out from output terminal 2, and this output signal is stored in one frame memory 3.
The output of the subtracter 4 which obtains a signal from one frame before through the subtracter 4 and subtracts the input signal from this signal is zero in the case of a correlated video signal, and is only uncorrelated noise. This noise is multiplied by a multiplication coefficient K in a multiplier 5, and added to the input signal in an addition R6, thereby canceling out the noise component.

Regarding the operating principle of these noise reducers, for example, as described in Takahiko Fukunuki [Image Digital Signal Processing J (P115 to P118) published by Nikkan Kogyo Shimbun, the unit delay corresponding to the delay of one frame. Operator Z
F-'', the transfer function of the recursive noise reducer shown in FIG. 2 is as follows.

H(Z) = (1-K) / (1-KZp'')
(1) This characteristic is a low-pass filter in the time direction (between one frame), and the frequency characteristic is as shown in FIG.

However, there is movement in an actual image, and the moving part acts to cancel out the input signal in the same way as noise, so the moving part becomes temporally blurred. The multiplication coefficient K of the multiplier 5 is optimally changed within the range of O≦≦1 in order to suppress this blur within the visual afterimage range and not cause visual disturbance.

That is, in the stationary part, even if the value is set to 1 and noise is reduced, no blurring will occur in principle. For the video section, set it to 1 + O to prevent blurring and give up on noise reduction.

As is well known, a general NTSC composite video signal uses a color subcarrier signal fsc as a color signal (for example, R-Y, B-Y, or 1.Q).
A carrier color signal (hereinafter referred to as a C signal) subjected to quadrature two-phase balanced modulation is superimposed on a luminance signal (hereinafter referred to as a Y signal).

Frequency もS of color subcarrier signal. As is well known, if the horizontal frequency is 壬□, then it becomes ChiS. = 455xヂ, /2-227,
5f, which is 0.5 (because there is a fraction of H, the phase of the color subcarrier signal is reversed in the vertical direction on the screen for each consecutive horizontal scanning line, and one frame has 525 scanning lines, which is an odd number. It goes around in two frames and has the same phase.

That is, since the scanning line goes around in one frame, the Y signal is a signal that goes around in one frame, but the C signal goes around in two frames. Therefore, the noise reducer circuit for the composite video signal needs to correlate with the signal two frames before.

FIG. 4 is a diagram showing a conventional cyclic noise reducer circuit. The same parts as in FIG. 2 are indicated by the same reference numerals. The difference is that the 1-frame memory portion is composed of a first 1-frame memory 7 and a second 1-frame memory 8, and the input signal is subtracted from the signal of a total of 2 frames before. The transfer function is as follows.

H(Z) ='(1-K)/(1-KF4)・
...(2) Also, the frequency characteristics are as shown in FIG.

(Problem to be Solved by the Invention) As mentioned above, the noise reducer circuit for the NTSC composite video signal needs to correlate with the signal two frames before, but since they are separated in time, there is little correlation. If the value of K is increased, blurring occurs, so it cannot be increased, and therefore, there is a problem that sufficient noise reduction cannot be achieved.

The present invention has been made with attention to the above points, and the coefficient K of the multiplier can be set to a large value by adding a simple circuit. It is an object of the present invention to provide a cyclic noise reducer circuit with enhanced noise reduction effect.

(Means for Solving the Problem) In order to achieve the above object, in a cyclic noise reducer circuit that obtains an output signal with reduced noise of an input signal, a first noise reducer circuit that receives the output signal as an input. a frame memory; a first subtracter that subtracts the input signal from the output of the first one-frame memory; an M2 one-frame memory that receives the output of the first one-frame memory; a second subtracter that subtracts the input signal from the output of the one-frame memory, a first filter that passes a signal that goes around in one frame, and a second filter that allows a signal that goes around in two frames to pass. and 0 to 1 in order to reduce noise without damaging the input signal as much as possible.
first and second multipliers each multiplying by an optimal multiplication coefficient between A second signal is obtained by passing the output of the second subtracter through the second filter and the second multiplier, and three of the first signal, second signal, and input signal are obtained. The present invention provides a cyclic noise reducer circuit characterized in that it includes an adder that adds signals to obtain the output signal.

(Embodiment) FIG. 1 is a diagram showing an embodiment of the cyclic noise reducer circuit of the present invention. The present invention separates and processes a signal that circulates in one frame (ie, Y signal) and a signal that circulates in two frames (ie, C signal), and its configuration will be described below.

In FIG. 1, the input signal to input terminal 1 is input to adder 15.
It is added to the other two signals at , and the output is led to output terminal 2 to become an output signal. This output signal is also input to a first one-frame memory 7, and the output of this first one-frame memory 7 is subtracted from the input signal from the input terminal 1 by a first subtracter 9, resulting in a Y-type signal. It is connected to an adder 15 via a filter 11 and a first multiplier 13 .

Moreover, the output of the first 1-frame memory 7 is simultaneously output to the second 1-frame memory 7.
The input signal from the input terminal 1 is subtracted by the second subtracter 10 via the frame memory 8, and the second
is connected to an adder 15 via a multiplier 14.

Next, the circuit operation will be explained with reference to FIG.

As for the operation for the Y signal component, the first subtracter 9 subtracts the input signal from the signal of one frame before, which is the output of the first one-frame memory 7, and the output is a difference value between one frame. This difference value between one frame includes a C signal whose phase is inverted between frames as well as uncorrelated noise components.

Y to pass only the Y signal to extract only the noise component
A first multiplier 13 multiplies the output by a multiplication coefficient optimal for the Y signal band by 1. The output of the first multiplier 13 (i.e., the first signal) is added to the input signal (i.e., the composite video signal) in the adder 15 to reduce noise components. The transfer function of the cyclic noise reducer circuit for this Y signal is expressed by the above equation (1).
The frequency characteristics become as shown in FIG.

As for the operation for the C signal component, the second subtracter 10 subtracts the two-frame previous signal and the input signal that have passed through the first one-frame memory 7 and second one-frame memory 8, and the output is the output between the two frames. It is a difference value. The difference value between these two frames includes an uncorrelated Y signal component (particularly a high frequency component) and a noise component. Since the high frequency components of the Y signal are separated in time, they have little correlation and cause blurring.

In order to remove this Y signal component, a C-type filter 12 that passes only the C signal is inserted into the output of the second subtracter 10 to extract only the noise component of the C signal. C to its output
A second multiplier 14 multiplies the optimal multiplication coefficient for the signal band by 2. The output of the second multiplier 14 (ie, the second signal) is added to the input signal (ie, the composite video signal) in an adder 15 to reduce noise components.

The transfer function for this C signal is the same as the equation (2) above, and therefore the frequency characteristics are as shown in FIG.

Therefore, the adder 15 adds three signals: the input signal, the first signal, and the second signal.

In the end, it becomes a noise reducer between frames that has a strong correlation with the Y signal that goes around in one frame, and the multiplication coefficient can be set to 1, increasing the noise reduction effect. Also, 2
2, which has little correlation with the C signal that goes around in a frame.
Although the processing is performed between frames, since there is no Y signal component and the color signal band is narrow, the multiplication coefficient can be set to a relatively large value of 2.

Also, the multiplication coefficient Kl that is optimal for the Y signal and C signal bands, respectively.
, can be independently set to 2, and the noise reduction effect can be enhanced for both the Y signal and the C signal.

Furthermore, it is effective to vary the value of K nonlinearly depending on the input signal level. FIG. 6 is a diagram showing an example of the characteristics of a multiplier, in which the slope of input versus output is K. Since the input to the multiplier is supposed to be a noise component as described above, its amplitude value is at a small level below a certain level.

Therefore, as shown in Figure 6, the threshold level AJ
:J, for the above input, components other than noise can be cut by setting =O.

Together with the above value of K, the threshold level A is set to Y
By setting the optimal values independently for each of the signal and the C signal, the noise reduction effect can be further enhanced.

(Effects of the Invention) The cyclic noise reducer circuit of the present invention has the above-described configuration, and is a simple circuit that can handle a signal that goes around in one frame (for example, the Y signal) and a signal that goes around in two frames (for example, the Y signal). For example, independent optimal multiplication coefficients can be set for both signals (for example, C signal). As a result, the noise reduction effect is enhanced for both signals without causing signal blurring, which is an excellent practical effect. ′

[Brief explanation of the drawing]

Fig. 1 shows an embodiment of the cyclic noise reducer circuit of the present invention, Fig. 2 shows the basic circuit of the cyclic noise reducer, and Fig. 3 shows the frequency characteristics of the basic circuit of the cyclic noise reducer. 4 is a diagram showing a conventional cyclic noise reducer circuit, FIG. 5 is a diagram showing frequency characteristics of a conventional cyclic noise reducer circuit, and FIG. 6 is a diagram illustrating an example of characteristics of a multiplier. be. 1... Input terminal, 2... Output terminal, 7... First one frame memory, 8... Second one frame memory,
9...first subtractor, 1o...second subtractor, 11
...Y type filter, 12...C type filter, 13.
...First multiplier, 14...Second multiplier, 15...
・Adder, K1. 2...multiplication coefficient.

Claims (1)

[Claims] A cyclic noise reducer circuit that obtains an output signal with reduced noise in an input signal, including a first one-frame memory that receives the output signal as an input, and an output from the first one-frame memory. a first subtracter that subtracts the input signal; a second one-frame memory that receives the output of the first one-frame memory; and subtracts the input signal from the output of the second one-frame memory. a second subtractor; a first filter that passes a signal that goes around in one frame; and a second filter that allows a signal that goes around in two frames to pass; and to reduce noise while preserving the input signal as much as possible. first and second multipliers each multiplying by an optimal multiplication coefficient between 0 and 1;
A first signal is obtained through a multiplier, and a second signal is obtained by passing the output of the second subtracter through the second filter and the second multiplier. 1. A cyclic noise reducer circuit comprising: an adder that adds three signals: a signal, a second signal, and the input signal to obtain the output signal.