JPH01128098A - Active matrix liquid crystal driving system - Google Patents

Abstract

PURPOSE: To make a defective pixel inconspicuous by inserting a period wherein a nonillumination level is supplied to signal lines in addition to a vertical blanking period while scanning line selecting operation is stopped in one frame period. CONSTITUTION: The period wherein the nonillumination level is supplied to the signal lines is inserted in addition to the vertical blanking period while the scanning line selecting operation is stopped in one frame period. Namely, the scanning operation is stopped and a signal of black level is supplied to the signal lines in 203rd-203nd horizontal periods. Consequently, the insertion of the period held at the nonillumination level makes a pixel, corresponding to a defective thin film transistor having its source and drain short-circuited, mean and dark, so the defective pixel can be made inconspicuous.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix liquid crystal driving system, and relates to a technique that is effective when used, for example, as a defect relief technique for TPT (FI film transistor).

[Conventional technology]

For example, Nikkei McGraw-Hill 198 has adopted a redundant configuration as a technology to increase the yield of liquid crystal display panels.
“Nikkei Electronics” dated December 15, 2006, page 193
- Page 209.

[Problem that the invention seeks to solve]

In the above redundant configuration, two TPT) transistors are provided for one pixel electrode, and if a defect occurs, a spare TPT transistor is provided.
Switch to . In this configuration, one TPT transistor is used.
Since it is necessary to form a spare TPT transistor and a scanning line electrode for one pixel electrode, the aperture ratio is sacrificed. Furthermore, since laser trimming technology is used to repair defects, the number of manufacturing processes and equipment increases.

An object of the present invention is to provide an active matrix drive system that can substantially repair defects in TPT transistors with a simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in addition to the vertical blanking period, a period in which a non-lighting level is supplied to the signal line is inserted with the scanning line selection operation stopped during one frame period.

[For production]

According to the above-mentioned means, by inserting a period in which the lighting is at a non-lighting level in one frame, the source.

Since pixels corresponding to defective TFT transistors whose drains are short-circuited can be averaged and darkened, defective pixels can be made less noticeable.

〔Example〕

FIG. 1 shows a timing diagram of an embodiment for explaining a driving method of a color liquid crystal display panel having an active matrix configuration.

In the color display device used in this embodiment, one frame period consists of 304 horizontal periods even though there are 200 color lines of the three primary colors, and the first A vertical synchronizing signal VSYN is generated in synchronization with the horizontal period. 30th of previous frame
The period from horizontal period No. 3 to the second horizontal period of the frame is a vertical retrace period. Therefore, the display operation in one frame is performed in 200 horizontal periods corresponding to 1 to 200 lines from the third horizontal period to the 202nd horizontal period, and the remaining 100 horizontal periods are used for defect relief. blanking period. In other words, during the 203rd to 302nd horizontal periods, the scanning operation is stopped and a black level (non-lighting level) signal is supplied to the signal line.

One horizontal period is defined by the horizontal synchronizing signal H3YH, and as shown enlarged in the figure, while the display timing signal DST is at a high level, color display data consisting of R, G, and B is displayed. It is considered valid display data,
Other than that, it is treated as horizontal retrace data (displayed in black). The above valid display data includes red (R), green (G) and blue (B).
) each consists of 640 dots (bits).

Therefore, the display timing signal DST is not formed from the 203rd period to the vertical blanking period.

Among defects in transistors (TPT), those that do not turn on are not noticeable as defects because the corresponding pixels are not lit (black display). On the other hand, if the drain and source of the transistor (TPT) are short-circuited, the level of the signal line electrode is always transmitted to the pixel electrode, resulting in a bright display depending on the supplied signal, which is an eyesore. becomes. In particular, when the surrounding display is close to black, if there is a defect such as the one described above, only that part will display brightly, which will be extremely annoying to the eyes.

In this embodiment, focusing on this, the 203rd to 302nd frames are set during one frame period as described above.
An extra horizontal period of be done. In this configuration, even if, in the worst case, a signal at the lighting level is transmitted to the signal line to which a defective pixel is connected during the display period, the black level does not change during the blanking period inserted thereafter. Reportedly. On the other hand, in a pixel in which such a defect as described above does not exist, the TFT transistor maintains an off state in response to the stop of the scanning operation, and retains the display data written in the display period. As a result, only for the defective pixels mentioned above,
The signal in the display period and the black level in the blanking period are averaged, and a brightness intermediate between them is displayed. Therefore, even in the worst case like '' above, the defect can be made less noticeable.

Incidentally, in the above color display panel, it is necessary to supply each color data of R (red), green (G) and blue (B) each consisting of 640 dots in one horizontal period. The liquid crystal display frame frequency depends on the data transfer rate of an X (signal line) drive circuit that performs serial/parallel conversion of the color data. For example, the rHD66 sold by Hitachi has a maximum transfer speed of 6MH2.
When using 106J, the frame frequency f is calculated using the following formula (1
) is determined by

f=1/ (1/6MHz)X (640/4)X (
200x3) = 62.5H2...(1) Here, the second term of the denominator, 640/4, means that the color data is serially transferred in units of 4 bits, and the third term 200X3 means that three primary color lines consisting of RlG and B constitute one color tod (line). However, as described above, actual lines in one frame require display time for 300 lines even though there are 200 pixel rows. Therefore, the actual frame frequency of the color display device to which this embodiment is applied is calculated using the following formula (2
)become that way.

f' = 1/(1/6 MHz)
(640/4)X(300x3)', 41.7Hz ---・12) As mentioned above, if the frame frequency f is only 41.7Hz, the liquid crystal It is necessary to write color data using both positive and negative polarities in order to drive the AC drive, and the actual frame frequency f' is further reduced to about 20.8 Hz, which is half of the above frame frequency f'. Image quality deteriorates.

In order to prevent such a decrease in frame frequency, a color display device that employs the above driving method has the following configuration.

FIG. 2 shows a block diagram of an embodiment of a color display "AM" to which the present invention is applied.

The color display device of this embodiment uses a color liquid crystal display panel LCD with an active matrix configuration. Although not particularly limited, the color liquid crystal display panel LCD has 640 dots x 640 dots, the details of which are shown in FIG.
Display of 200 lines of color pixels is possible. One line consists of a combination of three horizontal striped red, green, and blue color filters, corresponding to Y1 to Y3, Y4 to Y6, which are exemplarily shown.
. . . . Y selection (scanning) lines are provided, such as Y598, Y599, and Y2O2.

Further, signal lines X1 to X640 are arranged in the vertical direction. Therefore, the color liquid crystal display panel LCD has 600 Y selection lines in the vertical direction as described above, and the total number of pixels (vixels) is 640×600.

In FIG. 2, a color display device is provided with color display data consisting of R, G, and B. Eight colors (white,
Display of color pixels (including black) is possible. The dock clock signal CLK is supplied in synchronization with the display data R, G, and B. The display timing signal DST is a timing signal that displays visible information (valid display data) among display data when it is set to high level, and sets it as a horizontal retrace period when it is set to low level. The horizontal synchronization signal H3YN is a timing signal that controls one line, and the vertical synchronization signal VSYN is a timing signal that controls one frame.

The serial/parallel conversion circuit SPC receives the three color display data R, G, and B, and converts the color display data RS, which are serially input in synchronization with each other, in accordance with the dock clock signal CLK and the display timing signal DST.
G and B are each changed to 4-bit parallel data. These 4-bit parallel data are sent to the write memory selection circuit (hereinafter simply referred to as a multiplexer) MP.
Supplied to the input of Xl.

The multiplexer MPXI selectively writes the color display data converted into 4-bit parallel data into the first line memory LMI or the second line memory LM2 in accordance with a control signal R/W, which will be described later. Supplied to the input terminal.

The first and second line memories LMI and LM2 each have a storage capacity for storing color display data corresponding to one line of the color liquid crystal display panel LCD. That is, the display panel LCD is horizontally 640
To wait for the dot, a storage capacity of 640 x 3 bits is required. Since the line memories LMI and LM2 receive parallel data formed by the serial/parallel conversion circuit SPC as described above, memory access is performed in units of 4×3 bits. Therefore, the line memories LMI and LM2 each have a value of 0 to 1, as described later.
59 addresses. Although not particularly limited, static RAM (random access memory) is used as the line memories LMI and LM2. Instead of this configuration, it is also possible to use dynamic memory cells. This is because the line memories LMI and LM2 alternately perform a write operation and three read operations every horizontal period, as described later. Since such write and read operations are always performed at extremely short time intervals as described above, refresh operations are also constantly performed, and even when using dynamic memory cells, special refresh operations cannot be achieved. Since it is no longer needed, memory access can be performed in the same way as when using a static type memory cell. In this way, the line memories LMI and LM2 have a small storage capacity, and together with this, the occupied area can be further reduced.

A successive memory selection circuit (hereinafter referred to as a multiplexer) MPX2 is provided on the read output terminal side of the first and second line memories LM1 and LM2. This multiplexer MPX2 performs a switching operation complementary to the write multiplexer MPXI. For example, when the writing multiplexer MPXI outputs the control signal R/
When transmitting parallel display data to one line memory LMI (or LM2) in accordance with W, the multiplexer MPX2 used for reading is transmitted to the other line memory LM.
2 (or L M ], ) is selected and output.

The write control circuit WC receives the don't clock signal CLK,
Display timing signal DST and horizontal synchronization) signal HS Y
N, it generates the control signal R/W and the address signal WA for writing. In addition, the successive control circuit RC is
Upon receiving the horizontal synchronizing signal H5YN, a read address signal RA and a color selection signal C8 consisting of 2 bits are generated.
generate.

For example, if the control signal R/W is at a high level by the write control circuit WC, the multiplexer MPXI selects the first line memory LMI. Read/write control circuit RWC
is the write control circuit W according to the control signal R/W.
The write address signal WA generated in C is outputted as the address signal A1 of the line memory LMI. As a result, the color display data R, G, and B consisting of the three primary colors serially input for one line can be stored in the line memory L.
Written to MI.

On the other hand, the read address signal RA generated by the succession control circuit RC is transmitted as the address signal A2 of the second line memory LM2 by the read/write control circuit RWC. As a result, the light memory LM2 performs a read operation and supplies the stored color display data to the color selection circuit C3EL through the multiplexer MPX2.

Since the three primary color data RSG and B are output in parallel from the line memory LM2 in units of 4 bits as described above, the color selection circuit C5EL selects the order of R, G, and B according to the color selection signal C8. output in chronological order.

In this embodiment, in order to equivalently increase the frame frequency, each color data that is divided into colors and output serially is divided into two for each color by the divided data control circuit DDC, although this is not particularly limited. be divided. Correspondingly, the X drive circuits XDVL and XDVR are also divided into two. That is, the display screen of the color liquid crystal display panel LCD is divided into two parts, the apparent jonin (L) and the right (R), and the XvL dynamic circuits XDVL and XDVR are provided corresponding to each part. In this configuration, although the color liquid crystal display panel has 640 signal line electrodes, the X drive circuits XDVL and XDVR do not have display data driving capability corresponding to half of that number, 320 signal line electrodes. Since the two devices are configured to take in divided display data at the same time, the transfer speed of the display data can be doubled from the perspective of the liquid crystal display panel LCD. In other words, the time required to capture display data for one line can be cut in half.

The timing control circuit TC receives the display timing signal D.
ST and the vertical synchronization signal VSYN, it forms a data shift clock signal DSC and a line clock signal LCK necessary for the operation of the X drive circuits XDVL and XDVR and the Y drive circuit YDV. In addition, the timing control circuit T
C generates a line head clock signal LFS given to the Y drive circuit YDV. The Y drive circuit YDV uses the high level of the clock signal LFS as the line clock signal L.
It is taken in at the falling edge of CK and the scanning line Y1 is set to high level. After that, in synchronization with the falling edge of the line clock signal CLK, the high level is set to Y2, Y
3...Perform a vertical scanning operation by shifting in accordance with Y2O2.

FIG. 4 shows the color liquid crystal display panel LCD-, its X drive circuits XDVL and XDVR, and its Y drive circuit Y.
DV is shown.

As described above, the color liquid crystal display panel LCD has color filters in the form of horizontal stripes, and one line is composed of three pixel columns consisting of R, G, and B pixels. The Y drive circuit YDV has Yl to Y2O as described above.
It has two scanning lines, takes in the line head clock LFS generated at the beginning of the frame, and forms the Y selection signal by shifting it in synchronization with the line clock signal LCK. Therefore, one horizontal display period is temporally divided into three as described later, and the X drive circuit
When 640 dots of R1 data is sent from L and XDVR, scanning line Y1 is selected, when G1 data is sent, scanning line Y2 is selected, and when Bl data is sent, scanning line Y1 is selected. Y3 is brought into the selected state. As a result, the color image data of the first line 1 is written to each pixel in one horizontal period. In the next horizontal period, when 640 dots of R2 data are sent out from the X drive circuits XDVL and XDVR, scanning line Y4 is placed in a selected state, and when G2 data is sent out, scanning line Y5 is placed in a selected state, When B2 data is sent out, scan line Y
6 is placed in the selected state. As a result, the color image data of the next line 2 is written to each pixel. Thereafter, in the same manner, color pixel data R up to the final line 200
200, G200. B200 is written to each pixel.

Furthermore, in this embodiment, for defect relief, the first
As shown in the figure, a dummy write period for an extra 100 lines is provided, and a black level signal as described above is supplied. During this time, all the scanning lines are placed in a non-selected state. As a result, one frame is written.

For AC driving of the liquid crystal, the same display data R1 and G as above are used.
1, B1-R200, G200. B200 is outputted from the X drive circuits XDVL and XDVR with its polarity inverted, and in synchronization with this, the same scanning line selection operation as described above is performed. Therefore, the liquid crystal display panel LCD having an active matrix configuration needs to spend two frames having the above-mentioned dummy write period in order to display one screen.

FIG. 4 shows a timing diagram for explaining an example of color display data written to the line memory LMI or LM2.

The serial/parallel conversion circuit SPC converts each color (R,,C
and B) serially input color display data, 4
Bifu) is converted into parallel data as a unit to form Old French parallel data. That is, the signals RO to R159, GO-0159, and BO to B159 correspond to each color in units of 4 bits, and the signals are connected to the line, memory LMI or LM.
2 will be written. As a result, a total of 160x4=640 bits of color display data are written for each color.

FIG. 5 shows an address map diagram of the line memories t, Mt, and M2.

In this embodiment, the write parallel data is 4 as described above.
Since it is input in units of ×3 bits, the line memory LM
I and LM2 each have addresses O to 159.

In this embodiment, in order to increase the frame frequency as described above, the X drive circuit uses X D V as described above.
It is divided into two parts like L and XDVR.

In order to cope with this, the signals RO to R79, GO-G79 and BO-B which should be made to correspond to the X drive circuit XDVL
79 is XN at even address 0, 2...158
Signal R8Q-R that should correspond to the dynamic circuit XD VR
I59, G30-Gl59 and BO0NB159 are respectively assigned to odd addresses 1.3...159. As a result, in the line memories LMI and LM2, left-hand data is stored in odd-numbered addresses, right-hand data is stored in even-numbered addresses, and one address stores 4
X3=12 bit color display data is stored.

FIG. 6 shows a timing diagram for explaining the read operation from the line memory LMI or LM2.

The address signal RA formed by the continuous control circuit RC controls the switching operation of the multiplexer MPXI and the read/write control circuit RW according to the level of the control signal R/W.
While the above writing is being performed on the line memory LMl (or LM2) by the read/write control circuit RWC, the other line memory LM2
(or LMl), and its read signal is output by switching multiplexer MPX2. At this time, the successive output control circuit RC generates an address signal RA so that the selected line memory LM2 (or LMI) is read out three times in one horizontal period. Therefore, successive parallel data passed through the multiplexer MPX2 is outputted three times as RO to R159, GO to G159, and BO to B159.

A 2-bit color selection signal C8 is generated in accordance with the number of readings by the successive control circuit RC. for example,
In the first reading, the color selection signal C8 is 0 (0
0), and the color selection circuit C3EL selects RO-R159 among the color display data consisting of the three primary colors as described above.
Output. In the second readout, the color selection signal c
s is set to 1 (01), and the color selection circuit C3EL selects GO among the color display data consisting of the three primary colors as described above.
-Output G159. In the third reading, the color selection signal C3 is set to 2 (10), and the color selection circuit C3EL outputs BO to B159 of the color display data consisting of the three primary colors as described above.

In addition, the line memories LMI and LM2 are divided into odd and even addresses, and each color display data RO to
Since R159, GO~G159, and BO-B159 are stored, read address signal RA is set to 0~
When generated in order like 159, RO and R80,
Alternate left and right color display data are output like R1 and R81. The divided data control circuit DDC once borders the left and right color display data corresponding to the X drive circuits XDVL and XDVR as described above, and
and supplies it to XDVR. For example, the serial transfer rate of the X drive circuits XDVL and XDVR is 6M as described above.
If H2, reading from the line memories LM1 and LM2 is performed at twice the speed.

The parallel color data divided as above is sent to the RO-R7 in the X drive circuits XDVL and XDVR, respectively.
9 and R80 to Rl59 are shifted in 4-bit units in synchronization with the data shift clock DSC, and when the import is finished, the color display data from X1 to X6
Line clock L divided into 40 color display data
Outputs in parallel in synchronization with CK. GO~G79, 080~G159 and Go~G? up to 9 and 080
The color display data up to G159 is taken in and outputted in the same manner as described above. However, Y drive circuit Y
Since the DV switches the selection line from Yl to Y2 and Y3 in synchronization with the line clock CLK, a display operation corresponding to each color line is performed.

In this embodiment, by using two line memories as described above, while display data is being written to one line memory, data is read from the other line memory to which data has already been written, and the display data is displayed. Since it operates, it only has a memory circuit with a memory capacity for two lines. Therefore, even a color display device with a large screen and high image quality as described above can be configured with a small number of memory circuits.

Furthermore, since the X drive circuit is divided into two, the time required for the transfer operation is halved. In other words, when looking at the entire display device, it is equivalent to doubling the transfer speed of the X drive circuit. Therefore, as is clear from the above description, the frame frequency can be as high as 125 Hz. As a result, a dummy write period for 100 lines is inserted for defect relief, the actual display operation is stopped, and a black level is supplied to the signal line during this period, and also for AC drive of the liquid crystal display panel LCD. Even if the same display data is written with positive and negative polarities, the frame frequency is approximately 41.7 Hz, which allows for higher and more stable image quality than that of home television receivers.

As a result, the frame frequency can be equivalently increased while using the existing X drive circuit, so that the defect relief method described above can be easily implemented only by changing the timing signal.

In this configuration, only one transistor (TPT) is provided for each pixel constituting the liquid crystal display panel, and accordingly, only one scanning line electrode is provided. Therefore,
Aperture ratio can be increased. Further, the process and equipment for special defect relief processing become unnecessary.

The effects obtained from the above examples are as follows. That is, (1) The source and drain are short-circuited by inserting a period in which a non-lighting level is supplied to the signal line in addition to the vertical blanking period with the scanning line selection operation stopped during one frame period. Since pixels corresponding to defective TFT transistors can be averaged and darkened, an effect can be obtained in that defective pixels can be made less noticeable.

(2) According to (1) above, only one transistor (TPT) is provided for each pixel constituting the liquid crystal display panel, and accordingly, only one scanning line electrode is provided. Therefore, it is possible to increase the aperture ratio and eliminate the need for a special process and equipment for defect relief processing.

(3) First and second line memories are provided to store display data equivalent to one line of the display panel, and the first and second line memories are alternately controlled for writing and reading, and the above-mentioned The display data read from the first or second line memory is divided into a plurality of divided X drive circuits and is supplied in parallel.

In this configuration, even if an existing X drive circuit is used, the frame frequency can be increased because the transfer speed can be equivalently increased. Therefore, it is possible to provide a frame that supplies a black level for defect relief without sacrificing display quality.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. The period for supplying the black level provided during one frame period for defect relief is as follows:
For example, a horizontal period twice as long as the display line may be provided in one frame, so that the horizontal period is half of that period. In this case, since the time period during which the black level is supplied can be made longer, defective pixels can be made even less noticeable. Even in this case, a frame frequency of 31.5 Hz can be ensured by using the display device shown in FIG. 2 above. In this way, if the proportion of frames that supply the black level is increased, the actual frame frequency will correspondingly decrease, so this can be compensated for by dividing the X drive circuit into three or more N pieces. That's fine. Alternatively, an X drive circuit with a higher transfer speed may be developed. Furthermore, the specific configuration of the memory control circuit that causes the two line memories to perform write/read operations alternately can take various embodiments.

The liquid crystal display panel may perform black and white (bright and dark) display in addition to the color display as described above.

The present invention can be widely used in liquid crystal driving systems having an active matrix structure.

〔Effect of the invention〕

The effects obtained by typical inventions disclosed in this application are as follows. That is, by inserting a period in which a non-lighting level is supplied to the signal line in addition to the vertical retrace period while the scanning line selection operation is stopped during one frame, a defective TFT whose source and drain are short-circuited is removed. Since pixels corresponding to transistors can be averaged and darkened, defective pixels can be made less noticeable.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a timing diagram for explaining an embodiment of a liquid crystal driving method according to the present invention, and FIG. 2 is a timing diagram for explaining an embodiment of a color display device to which the present invention is applied. FIG. 3 is a block diagram showing an embodiment of the color liquid crystal display panel, FIG. 4 is a timing diagram for explaining parallel data written to the line memory, and FIG. A memory map diagram showing one embodiment of the line memory, FIG. 6 is a timing chart for explaining parallel data read from the line memory.

Claims (1)

[Claims] 1. A period in which a non-lighting level is supplied to the signal line is inserted in addition to the vertical blanking period while the scanning line selection operation is stopped during one frame period. Active matrix liquid crystal drive system. 2. The display data supplied to the signal line is alternately transmitted between the first and second memory circuits each storing display data corresponding to one line of the liquid crystal display panel, and the first and second memory circuits. A memory control circuit that performs write and read operations, and display data read out from the first or second storage circuit are divided into a plurality of parts and each is supplied to the liquid crystal display panel for one line. 2. The active matrix liquid crystal driving system according to claim 1, wherein the active matrix liquid crystal driving system is formed by an X driving circuit divided into a plurality of parts that serially captures an image signal corresponding to the image signal and outputs it in parallel. 3. Claim 1, wherein the display data is color display data, and the liquid crystal display panel has horizontal stripe-shaped color filters of three primary colors.
Or the active matrix liquid crystal driving method described in item 2.