JPH01129366A - Master data forming device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a mask data generation device, and aims to simplify the control of mask processing in a system with a large data width. a mask pattern of the predetermined data length consisting of bits indicating whether or not to mask each bit of the data for use, and outputting data according to the mask pattern; and a mask pattern generating means for inputting a number of upper mask bits specifying how many bits to mask and a number of lower mask bits specifying how many lower bits to mask and outputting a corresponding mask pattern. Configure it so that

[Industrial application field]

The present invention relates to a mask data generation device.

In the field of image processing and the like, mask processing is used in which only data in a specific pixel area in an image is processed and other parts are not processed. Such mask processing is performed with reference to a mask pattern consisting of bits corresponding to each pixel. However, faster processing,
As the data width of the system is also expanding in accordance with the increase in memory capacity, the mask patterns corresponding to this are also becoming longer, making processing complicated. Therefore, there is a need for a technique that simplifies the control of mask processing in such a system with a large data width.

[Prior art and problems to be solved by the invention]

Conventionally, for example, when writing data only to a specific part of an area in an image memory and masking other parts, such division of the mask area is generally independent of the byte unit of writing to memory. Since it is set bit by bit, it was common to give a mask pattern corresponding to each bit of the memory from the outside, and write data to the memory by referring to the mask pattern. .

However, when the data width to access the memory is large, it is necessary to provide a mask pattern with a large data width each time a write is performed, which poses a problem in that control for mask processing becomes complicated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a mask data generation device that simplifies control of mask processing in a system with a large data width.

Means for Solving Problem C] In the mask data generation device of the present invention, the number of upper mask bits specifying how many upper bits of data to be newly written are to be masked, and the number of lower bits to be masked. Mask pattern generation means is provided for inputting the number of lower mask bits specifying whether to use the mask pattern and outputting a corresponding mask pattern.

[For production]

,..., If the number of bits of the mask pattern is m, the number of bits required to specify the number of upper mask bits and the number of bits required to specify the number of lower bits are log and m, respectively, and the total is 21ogzm When bit data is input, an m-bit mask pattern is internally generated by the mask pattern generation means. Therefore, when performing mask processing in a system with a data width m where m > 21 ogzm holds, the mask processing can be controlled by inputting a smaller number of bits.

〔Example〕

FIG. 3 shows how mask data is written in the image memory. In this figure, 30 is a memory area that corresponds to one screen in a bit map manner, 31 is an area for writing data whose contents are to be updated in the memory area 30, and the area 30 excluding the writing area 31 is The masked area is set to prohibit updating of data.

Writing (and reading) data into the memory area of FIG. 3 is performed in 1-byte units from one end of the area, for example, as indicated by 32 or 33 in the figure. At this time, for example, in the byte area 32, the part (bit) indicated by 32a is located in the mask area and is therefore prohibited from being updated, and the part (bit) indicated by 32b is located in the write area 31, so its contents is required to be updated. At this time, the mask pattern given corresponding to the 8-bit data given externally for updating this byte area 32 is composed of, for example, 0" for the partial bits 32a and "1" for the bits 32b. In FIG. 3, the byte area 32 is an example in which the upper bits 32a are masked, and the byte area 33 is an example in which the lower bits 33b are masked.

FIG. 1 is a block diagram of an embodiment of a mask data generation device according to the present invention. In this figure, 2 is a merge circuit, 3 is a memory, and 1 is a mask pattern generation circuit provided according to the present invention and corresponds to the above-described mask pattern generation means. That is, the mask pattern generation circuit 1 determines an upper mask focus number that specifies how many upper bits of data to be newly written are to be masked, and a lower mask bit number that specifies how many lower bits are to be masked. It inputs and outputs the corresponding mask pattern. For example, high-speed S
This can be realized using RAM (static RAM) or ROM.

In FIG. 1, the mask pattern generation circuit 1 and the merge circuit 2 constitute the mask data generation device of the present invention. The memory 3 is a target for writing mask data generated according to the present invention. Merge circuit 2
are write data given from the outside, a mask pattern output from the mask pattern generation circuit 1, and
The data read from the memory 3 is input. Here, the data read from the memory 3 is data already held in the memory 3 at the address where the output data of the merge circuit 2 is to be written. The above three types of data input to the merge circuit 2 have the same number of bits (data width), and each bit of the three types of data corresponds to each other.

The merging circuit 2 selects the content of any one of the corresponding focus of the write data and the corresponding bit of the data read from the memory 3 according to the content of each bit of the mask pattern. Output and write into the memory 3. Although not related to the present invention, the merging circuit is generally known and has a function of adding an ECC code after selecting the bits described above.

FIG. 2 shows an example of the correspondence between input data and output data of a mask pattern generation means such as the mask pattern generation circuit 1 of FIG. 1. In FIG.

In FIG. 2, each input of the number of upper mask bits and the number of lower mask bits from the top row is shown as 3 bits representing a 3-digit binary number, and the bottom row shows 8 bits corresponding to each input in the upper row.
An example of a bit mask pattern output is shown. In the figure, "X'" indicates that it can be either "O" or "1". In the example in Figure 2, an 8-bit mask pattern is obtained by inputting 6 bits, but if the data width increases further, , the effect of reducing the number of input bits becomes even greater.For example, if 1
To achieve 6-bit output, the input is 21ogz16=
To achieve an output of 8 (bits) and 32 pins, the input is 21ogz32 = 10 (bits), and to achieve an output of 64 bits, the input is 21ogz64 = 12 (
bit) would be fine. Therefore, according to the mask data generation device having the configuration shown in FIG. 1, the control input for mask processing is simplified, and the effect becomes more noticeable as the data width of the system is expanded.

〔Effect of the invention〕

According to the mask data generation device of the present invention, control input for mask processing is simplified, and the effect becomes more noticeable as the data width of the system is expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the mask data generation device according to the present invention, FIG. 2 is a diagram showing an example of input/output of the mask pattern generation means, and FIG. 3 is an explanatory diagram of mask data writing in the image memory. It is. (Explanation of symbols) 1...Mask pattern generation circuit, 2...Merge circuit, 3...Memory, 30...Memory area, 31...Writing area.

Claims (1)

[Claims] 1. Input write data of a predetermined data length and a mask pattern of the predetermined data length consisting of bits indicating whether or not to mask each bit of the write data; Mask data generation means (2) that outputs data according to the pattern, a number of upper mask bits that specifies how many upper bits of the write data are to be masked, and a lower mask that specifies how many lower bits of the write data are to be masked. 1. A mask data generation device comprising: mask pattern generation means (1) for inputting a number of bits and outputting a corresponding mask pattern. 2. The mask data generation means (2) inputs the data already written in the position where the output data is to be written and the write data, and generates the contents of each bit of the mask pattern. 2. The mask data generation device according to claim 1, which selects and outputs either the corresponding bit of the write data or the corresponding bit of the already stored data, depending on the write data.