JPH01129449A - Multichip module and module substrate therefor - Google Patents

Multichip module and module substrate therefor

Info

Publication number
JPH01129449A
JPH01129449A JP62287391A JP28739187A JPH01129449A JP H01129449 A JPH01129449 A JP H01129449A JP 62287391 A JP62287391 A JP 62287391A JP 28739187 A JP28739187 A JP 28739187A JP H01129449 A JPH01129449 A JP H01129449A
Authority
JP
Japan
Prior art keywords
inspection
chip
input
multilayer wiring
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62287391A
Other languages
Japanese (ja)
Inventor
Kunio Matsumoto
邦夫 松本
Takanobu Noro
野呂 孝信
Naoya Isada
尚哉 諌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62287391A priority Critical patent/JPH01129449A/en
Priority to US07/271,677 priority patent/US4922377A/en
Publication of JPH01129449A publication Critical patent/JPH01129449A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/877Bump connectors and die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve a module function such as the increase of computing speed, to eliminate the need for a special cooling system at the time of inspection and to simplify an inspection process by forming a pad for changing inspection-technique onto the rear of a substrate and a power bus onto the surface of the substrate. CONSTITUTION:Since pads 50 for changing inspection-technique are arranged onto the rear of a substrate, chips 10 can be disposed in density higher than the pads have been arranged around the chips 10 by 40-50%. On inspection, a probe for inspection can be connected from the rear direction or the substrate, and a module can be inspected under the state of the assembled module. Consequently, a special cooling system need not be prepared on inspection. The probe for inspection is positioned easily to the pads 50 for changing inspection- technique disposed on a plane. The easy positioning of the probe for inspection also results in the connection of a technique varying wiring 60. For arrange the pads 50 for changing inspection-technique onto the rear of the substrate, input/output pins 35 are placed around a module substrate 30 and a power system onto the surface of the substrate as power buses 40.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数の半導体素子(以下、LSIチップという
)を搭載したマルチチップモジュール及びLSIチップ
を相互接続するマルチチップモジュール基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-chip module mounting a plurality of semiconductor elements (hereinafter referred to as LSI chips) and a multi-chip module substrate for interconnecting the LSI chips.

〔従来の技術〕[Conventional technology]

複数のLSIチップ(単にチップとも略称する)を相互
接続するモジュール基板構成の従来例として米国特許第
4302625号及び高密度実装技術、高密度多層基板
の応用(サイエンスフォーラム、昭和61年3月15日
、第196頁から第197頁)記載の多層セラミック基
板を挙げることができる。
U.S. Patent No. 4,302,625 and application of high-density mounting technology and high-density multilayer substrate (Science Forum, March 15, 1988) as a conventional example of a module board configuration that interconnects multiple LSI chips (also simply called chips) , pages 196 to 197).

この従来例では、LSIチップ相互接続用多層セラミッ
ク基板において、検査・技術変更パッドをチップ搭載面
(以下、基板表面という)に設け。
In this conventional example, an inspection/technical change pad is provided on the chip mounting surface (hereinafter referred to as the substrate surface) in a multilayer ceramic substrate for LSI chip interconnection.

入出力及び給電ピンをチップ搭載裏面(以下、載板裏面
という)に載置した構成となっている。また、チップの
放熱のための冷却体がチップ背面に熱接続できる構成と
なっている。
It has a configuration in which input/output and power supply pins are placed on the back surface of the chip mounting board (hereinafter referred to as the back surface of the mounting board). Furthermore, the configuration is such that a cooling body for dissipating heat from the chip can be thermally connected to the back surface of the chip.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来実装構成では、検査・技術変更用パッドがLS
Iチップ周辺の基板表面に略チップ信号端子数だけ配置
されているので、多端子化傾向にあるLSIチップの実
装では、検査・技術変更用パッド領域の確保のためにチ
ップの実装密度を犠牲にしなければならなかった。
In the above conventional mounting configuration, the pad for inspection and technology change is LS.
Approximately the same number of chip signal terminals are arranged on the board surface around the I chip, so when mounting LSI chips, which tend to have more terminals, it is necessary to sacrifice chip mounting density in order to secure pad area for inspection and technology changes. I had to.

また、モジュール検査時においては、検査用プローブを
検査・技術変更パッドに接続させるために、チップ背面
に熱接続されるべき冷却体をはずす必要があった。その
代り、検査用プローブの障害にならない特別の検査時冷
却システムを用意しなければならなかった。
Furthermore, during module testing, in order to connect the testing probe to the testing/technology change pad, it was necessary to remove the cooling body that should be thermally connected to the back surface of the chip. Instead, a special test cooling system had to be provided that would not interfere with the test probe.

本発明の目的は、上記した(1)検査・技術変更用パッ
ド領域確保のためのチップ実装密度低下、及び(2)モ
ジュール検査時における検査時冷却システムの要求の2
つの問題を解決することにある。
The purpose of the present invention is to meet the above-mentioned (1) reduction in chip mounting density to secure pad areas for inspection and technology changes, and (2) requirements for a cooling system during inspection during module inspection.
The aim is to solve one problem.

つまり1本発明の第1の目的は、LSIチップが高密度
に搭載され、かつモジュール検査時に特別のチップ冷却
システムを要せず、実使用時の冷却システムのままの状
態で容易に検査可能なマルチチップモジュールを提供す
ることにあり、第2の目的は、上記マルチチップモジュ
ールの使用に好適なモジュール基板を提供することにあ
る。
In other words, the first object of the present invention is to enable LSI chips to be mounted at high density and to easily test the module without requiring a special chip cooling system during module testing, with the cooling system as it is in actual use. A second object of the present invention is to provide a multi-chip module, and a second object is to provide a module substrate suitable for use with the multi-chip module.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、基板裏面に検査・技術変更用パッド〔と入
出力ピン(端子)〕を、基基板面に電源バス(給電端子
)を設けることにより、達成される。
The above object is achieved by providing a pad for inspection and technology change [and input/output pins (terminals)] on the back surface of the substrate, and a power supply bus (power supply terminal) on the surface of the substrate.

以下に本発明マルチチップモジュールの特徴点を列挙し
、さらに具体的に説明する。
Features of the multi-chip module of the present invention will be listed below and explained in more detail.

(1)信号入出力端子、給電端子及び検査・技術変更用
パレドとを有する多層配線基板と、前記基板に搭載され
、かつその背面に冷却手段の設けられた複数の半導体L
SIチップとから成るマルチチップモジュールにおいて
、前記多層配線基板の表面には、その背面に冷却手段の
設けられたiII記半導体LSIチップが素子接続部を
通して電気的に接続配設されると共に、その周縁には電
源接続部を通して給電端子が配設されており、前記多層
配線基板の裏面には、前記半導体LSIチップに接続さ
れた入出力端子と検査・技術変更用パッドパターンとが
配設されていることを特徴とする。
(1) A multilayer wiring board having a signal input/output terminal, a power supply terminal, and a pallet for inspection and technology changes, and a plurality of semiconductor L mounted on the board and provided with a cooling means on the back side thereof.
In a multi-chip module consisting of an SI chip, on the surface of the multilayer wiring board, a semiconductor LSI chip according to III, which is provided with a cooling means on its back surface, is electrically connected through an element connection portion, and the peripheral edge thereof is A power supply terminal is arranged through a power supply connection part, and an input/output terminal connected to the semiconductor LSI chip and a pad pattern for inspection and technology change are arranged on the back side of the multilayer wiring board. It is characterized by

(2)上記検査・技術変更用パッドには、対応する上記
半導体LSIチップの各入出力端子に接続するリードと
、隣接するL S Iチップ相互間を電気的に接続する
リードとが上記多層配線基板を介して接続されているこ
とを特徴とする。
(2) The above-mentioned inspection/technology change pad has leads connected to each input/output terminal of the corresponding above-mentioned semiconductor LSI chip, and leads that electrically connect adjacent LSI chips to the above-mentioned multilayer wiring. It is characterized by being connected via a board.

(3)上記多層配線基板の裏面の主面には検査・技術変
更用パッドパターンが設けられ、その周縁に入出力端子
群が配設されて成ることを特徴とする。
(3) A pad pattern for inspection and technology change is provided on the main surface of the back side of the multilayer wiring board, and a group of input/output terminals are arranged on the periphery of the pad pattern.

次に、本発明マルチチップモジュール用基板の特徴点を
列挙し、さらに具体的に説明する。
Next, the features of the multi-chip module substrate of the present invention will be listed and explained in more detail.

(1)半導体LSIチップ搭載面のLSIチップ配設該
当周縁部に給電端子を設け、前記L S Iチップ搭載
、S面には検査・技術変更用パッドパターンと入出力端
子とを設けると共に、少なくとも前記検査・技術変更用
パッドパターンに接続する前記L S Iチップの電極
からのリードと隣接する前記LSIチップ相互間を電気
的に接続するリードとを内在させた多層配線構造体から
成ることを特徴とする。
(1) A power supply terminal is provided on the periphery of the semiconductor LSI chip mounting surface where the LSI chip is mounted, and a pad pattern for inspection and technology change and an input/output terminal are provided on the LSI chip mounting surface and the S surface. It is characterized by comprising a multilayer wiring structure including leads from the electrodes of the LSI chips connected to the pad patterns for inspection and technology changes and leads electrically connecting the adjacent LSI chips. shall be.

(2)上記検査・技術変更用パッドには対応する上記半
導体LSIチップの各入力端子に接続するリードと、隣
接するLSIチップ相互間を電気的に接続するリードと
が接続されていることを特徴とする。
(2) The inspection and technology change pads are connected to leads that connect to each input terminal of the corresponding semiconductor LSI chip and leads that electrically connect adjacent LSI chips. shall be.

(3)上記検査・技術変更用パッドパターンの周縁に入
出力群を設けたことを特徴とする。
(3) An input/output group is provided at the periphery of the pad pattern for inspection and technology change.

(4)上記多層配線構造体には少なくとも給電層、信号
入出力層及び接地層の三層が積層して成ることを特徴と
する。
(4) The multilayer wiring structure is characterized in that at least three layers, a power supply layer, a signal input/output layer, and a ground layer are laminated.

(5)上記多層配線構造体は配線パターンの施されたセ
ラミックスの積層板から成ることを特徴とする。
(5) The multilayer wiring structure is characterized in that it is composed of a ceramic laminate plate provided with a wiring pattern.

(作用〕 まず、基板表面のLSIチップ周辺に設けられていた検
査・技術変更用パッドを基板裏面に配置し、代りに基板
表面のチップ周辺に電源バス(給電端子)を設けること
について考える。本発明においては、電源バスに使われ
る導体の厚さを数mm以下にしてもその高さ方向に制限
がないため、導体高さを十分高く確保でき、給電経路の
抵抗を小さく抑えることは可能である。一方、検査・技
術変更用パッドは基板表面よりも基板裏面に配置した方
がチップ搭載面積だけ余裕ができ、より多くの検査・技
術変更用パッドを配置できる。すなわち、検査・技術変
更用パッド数を十分確保しつつ。
(Function) First, consider placing the pads for inspection and technology changes that were provided around the LSI chip on the front surface of the board on the back side of the board, and instead providing a power bus (power supply terminal) around the chip on the front surface of the board. In the invention, even if the thickness of the conductor used in the power supply bus is reduced to several millimeters or less, there is no limit to its height, so the conductor height can be ensured sufficiently high and the resistance of the power supply path can be kept low. On the other hand, if the pads for inspection and technology changes are placed on the back side of the board rather than the front surface of the board, there will be more room for the chip mounting area, and more pads for inspection and technology changes can be placed. While ensuring a sufficient number of pads.

LSIチップを高密度に実装することが可能となる。ま
た、モジュール検査時においては、基板裏面から検査用
プローブを検査・技術変更バッドに接続させることがで
き、素子背面に熱接続されている冷却体をはずす必要は
なく特別な検査時冷却システムは不要となる。
It becomes possible to mount LSI chips with high density. Additionally, during module inspection, the inspection probe can be connected to the inspection/technology change pad from the back side of the board, and there is no need to remove the cooling body that is thermally connected to the back of the element, so there is no need for a special cooling system during inspection. becomes.

〔実施例〕〔Example〕

以下1本発明の一実施例を第1図及び第2図により説明
する。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第1図は本発明の一実施例を示すマルチチップモジュー
ルの断面図、第2図は同斜視図である6第1図及び第2
図において、 10は搭載すべきLSIチップ、20は
チップ10を冷却するための冷却体、21は冷却体20
に設けらJlた冷媒路、40はチップ10への給電用電
源バス、41は電源バス40の異種電圧印加用電源還体
、42は電源導体41相互の絶縁を図るための絶縁層、
30はモジュール基板、33はモジュール基板30にチ
ップ10を接続するための素子接続部、34はモジュー
ル基板30に電源導体41を接続するための電源接続部
、 31はチップ10への給′6用電源層、32はチッ
プ10相互を配線する配線層、5゜はモジュール基板3
0の裏面に配置された検査・技術変更バッド、51はチ
ップ10の(1号線を検査・技術変更パッド50に導く
ための貫通導体、52は検査・技術変更バッド50と配
線層32を結ぶための経由導体、35は他のモジュール
あるいは外部との信号接続用入出力ピン、60は検査・
技術変更バッド50 、kに接続された技術変更布線で
ある8 第1図及び第2図から分かるように、検査・技術変更用
パッド50を基板裏面に配置することにより、従来、チ
ップ10周辺に配置されていたときと比較しチップ10
を40〜50%増の高密度に配置可能となる。また、検
査時においては、検査用プローブを基板裏面方向から接
続可能となり1組み立てられたモジュール状態で検査で
きる。このため、検査時に特別な冷却システムを用意す
る必要はない。さらに、平面配置された検査・技術変更
パッド50へは検査用プローブの位置決めが容易となる
などの長所が挙げられる。このことは、技術変更布線6
0の接続をも容易ならしめる。
Fig. 1 is a sectional view of a multi-chip module showing an embodiment of the present invention, and Fig. 2 is a perspective view thereof.
In the figure, 10 is an LSI chip to be mounted, 20 is a cooling body for cooling the chip 10, and 21 is a cooling body 20.
40 is a power supply bus for supplying power to the chip 10, 41 is a power supply return body for applying different voltages of the power supply bus 40, 42 is an insulating layer for insulating the power supply conductors 41 from each other,
30 is a module board, 33 is an element connection part for connecting the chip 10 to the module board 30, 34 is a power supply connection part for connecting the power supply conductor 41 to the module board 30, and 31 is for supply '6 to the chip 10. power supply layer; 32 is a wiring layer that interconnects the chips 10; 5° is a module board 3;
0, 51 is a through conductor for guiding line 1 of the chip 10 to the inspection/technical change pad 50, 52 is a through conductor for connecting the inspection/technical change pad 50 and the wiring layer 32. 35 is an input/output pin for signal connection with other modules or the outside, 60 is an inspection/output pin.
As can be seen from FIGS. 1 and 2, by arranging the pad 50 for inspection and technology change on the back surface of the substrate, the area around the chip 10 has been improved. Chip 10 compared to when it was placed in
can be arranged at a high density of 40 to 50%. Furthermore, during inspection, the inspection probe can be connected from the back side of the board, allowing inspection to be performed in a single assembled module state. Therefore, there is no need to prepare a special cooling system during inspection. Furthermore, the planar arrangement of the inspection/technology change pad 50 has the advantage that the inspection probe can be easily positioned. This means that technology change wiring 6
It also makes it easy to connect 0.

なお、本実施例では検査・技術変更用パッド50を基板
裏面に配置するために、入出力ピン35はモジュール基
板30の周辺に、電源系は電源バス40として基板表面
に載置する構成となっている。
In addition, in this embodiment, in order to arrange the pad 50 for inspection and technology change on the back side of the board, the input/output pins 35 are placed around the module board 30, and the power supply system is placed on the surface of the board as a power bus 40. ing.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、検査・技術変更用パッド領域を確保し
つつLSIチップ実装密度を向上させることができ、演
算速度の高速化等モジュール機能の向上が可能となる。
According to the present invention, it is possible to improve the LSI chip mounting density while securing a pad area for inspection and technology changes, and it is possible to improve module functions such as increasing calculation speed.

また、モジュール検査時において、特別な検査時冷却シ
ステムが不要となり、検査工程の簡素化等が図られる。
Further, during module inspection, a special inspection cooling system is not required, and the inspection process can be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のマルチチップモジュールの
断面図、第2図は同じく斜視図である。 図において。 10・・・LSIチップ 20・・・冷却体 30・・・モジュール基板 40・・・電源バス 50・・・検査・技術変更パッド 35・・・入出力ピン 60・・・技術変更布線 代理人弁理士  中 村 純之助
FIG. 1 is a sectional view of a multi-chip module according to an embodiment of the present invention, and FIG. 2 is a perspective view thereof. In fig. 10... LSI chip 20... Cooling body 30... Module board 40... Power bus 50... Inspection/technology change pad 35... Input/output pin 60... Technology change wiring agent Patent attorney Junnosuke Nakamura

Claims (8)

【特許請求の範囲】[Claims] 1.信号入出力端子、給電端子及び検査・技術変更用パ
ッドとを有する多層配線基板と、前記基板に搭載され、
かつその背面に冷却手段の設けられた複数の半導体LS
Iチップとから成るマルチチップモジュールにおいて、
前記多層配線基板の表面には、その背面に冷却手段の設
けられた前記半導体LSIチップが素子接続部を通して
電気的に接続配設されると共に、その周縁には電源接続
部を通して給電端子が配設されており、前記多層配線基
板の裏面には、前記半導体LSIチップに接続された入
出力端子と検査・技術変更用パッドパターンとが配設さ
れていることを特徴とするマルチチップモジュール。
1. a multilayer wiring board having a signal input/output terminal, a power supply terminal, and a pad for inspection/technical change;
and a plurality of semiconductor LSs each having a cooling means on its back surface.
In a multi-chip module consisting of an I-chip,
On the surface of the multilayer wiring board, the semiconductor LSI chip, which is provided with a cooling means on the back side thereof, is electrically connected through an element connection part, and at the periphery thereof, a power supply terminal is provided through a power supply connection part. A multi-chip module characterized in that input/output terminals connected to the semiconductor LSI chip and pad patterns for inspection and technology changes are arranged on the back surface of the multilayer wiring board.
2.上記検査・技術変更用パッドは、対応する上記半導
体LSIチップの各入出力端子に接続するリードと、隣
接するLSIチップ相互間を電気的に接続するリードと
が上記多層配線基板を介して接続されていることを特徴
とする特許請求の範囲第1項記載のマルチチップモジュ
ール。
2. In the above-mentioned inspection/technology change pad, leads connecting to each input/output terminal of the corresponding semiconductor LSI chip and leads electrically connecting adjacent LSI chips are connected via the multilayer wiring board. A multi-chip module according to claim 1, characterized in that:
3.上記多層配線基板の裏面の主面には検査・技術変更
用パッドパターンが設けられ、その周縁に入出力端子群
が配設されて成ることを特徴とする特許請求の範囲第1
項もしくは第2項記載のマルチチップモジュール。
3. Claim 1, characterized in that a pad pattern for inspection and technology change is provided on the main surface of the back side of the multilayer wiring board, and a group of input/output terminals are arranged on the periphery of the pad pattern.
The multi-chip module according to item 1 or 2.
4.半導体LSIチップ搭載面のLSIチップ配設該当
周縁部に給電端子を設け、前記LSIチップ搭載裏面に
は検査・技術変更用パッドパターンと入出力端子とを設
けると共に、少なくとも前記検査・技術変更用パッドパ
ターンに接続する前記LSIチップの電極からのリード
と隣接する前記LSIチップ相互間を電気的に接続する
リードとを内在させた多層配線構造体から成ることを特
徴とするマルチチップモジュール用基板。
4. A power supply terminal is provided at the periphery of the semiconductor LSI chip mounting surface where the LSI chip is arranged, and a pad pattern for inspection and technology change and an input/output terminal are provided on the back surface where the LSI chip is mounted, and at least the pad pattern for inspection and technology change is provided. 1. A multi-chip module substrate comprising a multilayer wiring structure including leads from electrodes of the LSI chips connected to the pattern and leads electrically connecting adjacent LSI chips.
5.上記検査・技術変更用パッドには対応する上記半導
体LSIチップの各入力端子に接続するリードと、隣接
するLSIチップ相互間を電気的に接続するリードとが
接続されていることを特徴とする特許請求の範囲第4項
記載のマルチチップモジュール用基板。
5. A patent characterized in that the inspection/technology change pads are connected to leads that connect to each input terminal of the corresponding semiconductor LSI chip and leads that electrically connect adjacent LSI chips. A multi-chip module substrate according to claim 4.
6.上記検査・技術変更用パッドパターンの周縁に入出
力端子群を設けたことを特徴とする特許請求の範囲第4
項もしくは第5項記載のマルチチップモジュール用基板
6. Claim 4, characterized in that a group of input/output terminals is provided at the periphery of the pad pattern for inspection and technology change.
The multi-chip module substrate according to item 5 or item 5.
7.上記多層配線構造体には少なくとも給電層、信号入
出力層及び接地層の三層が積層して成ることを特徴とす
る特許請求の範囲第4項、第5項もしくは第6項記載の
マルチチップモジュール用基板。
7. The multi-chip according to claim 4, 5 or 6, wherein the multilayer wiring structure is formed by laminating at least three layers: a power supply layer, a signal input/output layer, and a ground layer. Module board.
8.上記多層配線構造体は配線パターンの施されたセラ
ミックスの積層板から成ることを特徴とする特許請求の
範囲第7項記載のマルチチップモジュール用基板。
8. 8. The multi-chip module substrate according to claim 7, wherein said multilayer wiring structure is made of a ceramic laminate plate provided with a wiring pattern.
JP62287391A 1987-11-16 1987-11-16 Multichip module and module substrate therefor Pending JPH01129449A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62287391A JPH01129449A (en) 1987-11-16 1987-11-16 Multichip module and module substrate therefor
US07/271,677 US4922377A (en) 1987-11-16 1988-11-16 Module and a substrate for the module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62287391A JPH01129449A (en) 1987-11-16 1987-11-16 Multichip module and module substrate therefor

Publications (1)

Publication Number Publication Date
JPH01129449A true JPH01129449A (en) 1989-05-22

Family

ID=17716741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62287391A Pending JPH01129449A (en) 1987-11-16 1987-11-16 Multichip module and module substrate therefor

Country Status (1)

Country Link
JP (1) JPH01129449A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721299A (en) * 1989-05-26 1998-02-24 International Business Machines Corporation Electrically conductive and abrasion/scratch resistant polymeric materials, method of fabrication thereof and uses thereof
JP2010007306A (en) * 2008-06-25 2010-01-14 Takigen Mfg Co Ltd Pin tumbler lock operable by cylindrical key

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721299A (en) * 1989-05-26 1998-02-24 International Business Machines Corporation Electrically conductive and abrasion/scratch resistant polymeric materials, method of fabrication thereof and uses thereof
JP2010007306A (en) * 2008-06-25 2010-01-14 Takigen Mfg Co Ltd Pin tumbler lock operable by cylindrical key

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