JPH01129920U

JPH01129920U -

Info

Publication number: JPH01129920U
Application number: JP2407288U
Authority: JP
Priority date: 1988-02-25
Filing date: 1988-02-25
Publication date: 1989-09-05

Description

[Brief explanation of the drawing]

第１図から第３図はこの考案の一実施例を示す
図、第４図及び第５図は従来の例を示す図である
。１は基準クロツク回路、２は計算機、３はメモ
リ、４ａ，４ｂ，４ｃはアドレスバス、５はライ
ト信号、６はデータバス、７はアドレスカウンタ
、９はセレクタ、１０は同期回路、Ｄ_１〜Ｄｍは
周波数データ、ｆ_１〜ｆｍは動作周波数である。
なお、図中、同一符号は同一又は相当部分を示す
。 1 to 3 are diagrams showing an embodiment of this invention, and FIGS. 4 and 5 are diagrams showing a conventional example. 1 is a reference clock circuit, 2 is a computer, 3 is a memory, 4a, 4b, 4c are address buses, 5 is a write signal, 6 is a data bus, 7 is an address counter, 9 is a selector, 10 is a synchronization circuit, D ₁ - Dm is frequency data, and f ₁ to fm are operating frequencies.
In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

In an oscillation circuit that generates a rectangular waveform, there is a memory that stores a plurality of rectangular waveforms, a computer that stores the period and duty of the rectangular waveform in this memory in a program, and a computer that sequentially processes the rectangular wave data stored in the memory by the computer. It consists of an address counter that outputs data, and a synchronization circuit that synchronizes the rectangular wave data output from the memory by the address counter, and the period and duty of multiple consecutive rectangular waveforms can be arbitrarily set by a computer program. An oscillation circuit characterized by changing the oscillation circuit.