JPH0447768U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a specific example of the second clock generator in Figure 1, Figure 3 is a timing chart explaining the operations of Figures 1 and 2, and Figure 4 is a circuit diagram showing an example of a conventional waveform generator. , FIG. 5 is an explanatory diagram of a waveform generated by conventional clocks having the same frequency, and FIG. 6 is an explanatory diagram of a waveform generated by conventional clocks having different frequencies. 1, 2...memory, 3, 4...D/A converter,
8... Adder, 16... First clock generator, 1
7...Second clock generating section.

Claims (1)

[Claims for Utility Model Registration] A first memory in which first waveform data and trigger data are stored; a second memory in which second waveform data is stored; and a first memory that is read from the first memory. a first D/A converter that converts the first waveform data into an analog signal; a second D/A converter that converts the second waveform data read from the second memory into an analog signal; a first clock generator that supplies a first clock to a first memory and a first D/A converter; a second clock supplying a second clock having a different frequency from the first clock to the second memory and the second D/A converter;
and an adder that adds and outputs the analog signal converted and output from the first D/A converter and the analog signal converted and output from the second D/A converter. A waveform generator characterized by: