JPH0113206B2 - - Google Patents
Info
- Publication number
- JPH0113206B2 JPH0113206B2 JP56165187A JP16518781A JPH0113206B2 JP H0113206 B2 JPH0113206 B2 JP H0113206B2 JP 56165187 A JP56165187 A JP 56165187A JP 16518781 A JP16518781 A JP 16518781A JP H0113206 B2 JPH0113206 B2 JP H0113206B2
- Authority
- JP
- Japan
- Prior art keywords
- silver
- silicone
- electrodes
- multilayer ceramic
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
本発明はシリコーン被覆を有し、両端部に銀ま
たは銀―パラジウム合金,ニツケル及びスズ―鉛
合金からなる電極部を有する耐湿性の良好な積層
セラミツクコンデンサの製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a laminated ceramic capacitor having good moisture resistance and having a silicone coating and electrode parts made of silver or silver-palladium alloy, nickel or tin-lead alloy at both ends. It is something.
従来より、積層セラミツクコンデンサは電子回
路の小型化と相まつて小型大容量化が図られてき
ており、現在ハイブリツドIC用及びプリント基
板直付け用のチツプ部品としてその需要は急増し
ている。 Multilayer ceramic capacitors have traditionally been made smaller and larger in capacity as electronic circuits become smaller, and demand for them is currently rapidly increasing as chip components for hybrid ICs and for direct mounting on printed circuit boards.
この積層セラミツクコンデンサは、一般にセラ
ミツク誘電体とパラジウム及び/または白金の薄
膜層を交互に積層して得られる積層体に基づくも
のであり、内部の金属薄膜が誘電体を狭持する形
で並列回路を形成するように端部の銀または銀―
パラジウム合金電極と接続する構成をなしてい
る。この積層セラミツクコンデンサに使用される
誘電体の厚みは15〜100μm程度であり、このよう
な薄い誘電体平面に電極を設けて折りたたんだよ
うな構造をしている。 Multilayer ceramic capacitors are generally based on a laminate obtained by alternately laminating a ceramic dielectric and thin film layers of palladium and/or platinum, and form a parallel circuit in which the dielectric is sandwiched between the internal metal thin films. The ends of the silver or silver-
It is configured to be connected to a palladium alloy electrode. The thickness of the dielectric material used in this multilayer ceramic capacitor is approximately 15 to 100 μm, and the structure is such that electrodes are provided on a flat surface of such a thin dielectric material and folded.
一般に、コンデンサの静電容量は、
C=εε0S/t
であらわされる。ここで、εは真空の誘電率、ε0
は誘電体の比誘電率、Sは電極面積、及びtは電
極間距離を示す。したがつて、体積当りの容量を
考えると、
C/V∝1/t2(Vはコンデンサの体積)
となり、厚みの2乗に反比例する。そこで、単板
型のセラミツクコンデンサと積層セラミツクコン
デンサの体積当りの容量を比較すると、積層セラ
ミツクコンデンサの方が円板型セラミツクコンデ
ンサの厚みの約1/10以下にすることが可能である
から、約100倍以上の容量が同一体積で得ること
ができる。(尚、円板型セラミツクコンデンサで
は強度的に厚みを薄くすることが不可能だから、
現在では500μm前後が限度である。)
このように積層セラミツクコンデンサは小型か
つ大静電容量を有するものであり、電子回路の小
型化に適合しており、さらに電極にスズ及び鉛の
合金メツキをほどこすことにより、プリント基板
への直付けが容易にできるようになつてきてい
る。 Generally, the capacitance of a capacitor is expressed as C=εε 0 S/t. Here, ε is the permittivity of vacuum, ε 0
is the dielectric constant of the dielectric, S is the electrode area, and t is the distance between the electrodes. Therefore, considering the capacitance per volume, it becomes C/V∝1/t 2 (V is the volume of the capacitor), which is inversely proportional to the square of the thickness. Therefore, when comparing the capacitance per volume of a single-plate ceramic capacitor and a multilayer ceramic capacitor, the thickness of a multilayer ceramic capacitor can be reduced to about 1/10 or less of that of a disk-type ceramic capacitor, so it is approximately More than 100 times more capacity can be obtained with the same volume. (Please note that it is impossible to reduce the thickness of disc-type ceramic capacitors due to their strength.
Currently, the limit is around 500 μm. ) As described above, multilayer ceramic capacitors are small and have large capacitance, making them suitable for miniaturizing electronic circuits.Furthermore, by applying tin and lead alloy plating to the electrodes, they can be easily attached to printed circuit boards. Direct attachment is becoming easier.
しかしながら、このような積層セラミツクコン
デンサの欠点もいくつかあり、その欠点の一つ
は、誘電体厚みを薄くするために生ずる欠陥であ
る。すなわち、セラミツク自身もともと多結晶体
からなるもので、緻密な単結晶とは異なり、無数
の気孔を有している。このような気孔はまた均一
な大きさではなく、大きな気孔も存在する。この
気孔を小さく均一分布化することは一つの課題で
あり、積々研究されてはいるが、未だ十分とはい
えない。このような気孔の及ぼす影響としては、
耐湿性を弱くすることである。特に、ニツケルあ
るいはスズ―鉛合金メツキなどにより、電解液を
用いる工程において、電解質の残存などが問題と
なつたりする。電解質が残存すると、湿気が再び
浸透することにより絶縁抵抗が低下することがあ
る。このようなことは製品としての信頼性を著し
く損なうものであり、市場にて問題を発生するこ
とが少なくない。このため、特にメツキ電極を付
与する積層セラミツクコンデンサについては注意
を要したものであつた。 However, such laminated ceramic capacitors have several drawbacks, one of which is defects that occur due to the thinning of the dielectric material. That is, ceramic itself is originally a polycrystalline material, and unlike a dense single crystal, it has countless pores. Such pores are also not of uniform size, and large pores also exist. Making these pores small and uniformly distributed is one of the challenges, and although much research has been done, it is still not sufficient. The effects of these pores are as follows:
It weakens moisture resistance. In particular, in processes using electrolytes such as nickel or tin-lead alloy plating, residual electrolyte may become a problem. If the electrolyte remains, the insulation resistance may decrease due to re-penetration of moisture. Such a situation significantly impairs the reliability of the product and often causes problems in the market. For this reason, special attention must be paid to multilayer ceramic capacitors provided with plated electrodes.
本発明は以上の欠点を考慮し、種々の実験を通
して得られたものである。 The present invention was achieved through various experiments in consideration of the above drawbacks.
以下、本発明の詳細について実施例に基づき説
明する。 Hereinafter, details of the present invention will be explained based on examples.
<実施例>
チタン酸バリウム71.4重量部,ジルコン酸バリ
ウム20.4重量部,チタン酸カルシウム7.4重量部,
酸化亜鉛0.2重量部,二酸化マンガン0.15重量部,
酸化タングステン0.25重量部及び酸化アルミニウ
ム0.25重量部よりなる混合粉末に対して、エチル
セルローズを主体とするバインダーを用いてスラ
リーを作製し、40±2μmの厚みのシートをドクタ
ーブレード法を用いて成型した。このシートを一
定のサイズに打抜いた後、パラジウム電極を印刷
した。この電極印刷済みのシートを電極がクシ形
状になるように積重ねて圧着した後、3.6mm×1.8
mm×0.45mmの大きさに切断した。このチツプを
1370℃±20℃で2時間焼成して得た焼結体の両端
面に銀ペーストをほどこし、800℃で焼付けた。
このようにして作製された積層体の全面にシリコ
ーンを付着し、250〜300℃の範囲で4〜6時間熱
処理してシリコーンを重合させた後、その熱処理
済みの積層体を内径150mmのポリポツト内に投入
し95〜100r・p・mの回転速度にて30分間共ズリ
して両端部の銀電極部のシリコーンを除去した。
ついで、シリコーンの除去された両端部の銀電極
部にニツケルメツキを1〜2μm、さらにその上に
スズと鉛の合金メツキを1〜2μmほどこした。<Example> Barium titanate 71.4 parts by weight, barium zirconate 20.4 parts by weight, calcium titanate 7.4 parts by weight,
Zinc oxide 0.2 parts by weight, manganese dioxide 0.15 parts by weight,
A slurry was prepared using a binder mainly composed of ethyl cellulose from a mixed powder consisting of 0.25 parts by weight of tungsten oxide and 0.25 parts by weight of aluminum oxide, and a sheet with a thickness of 40 ± 2 μm was formed using a doctor blade method. . After punching out this sheet to a certain size, palladium electrodes were printed. After stacking and crimping the electrode-printed sheets so that the electrodes form a comb shape, 3.6 mm x 1.8
It was cut into a size of mm x 0.45 mm. This chip
Silver paste was applied to both end faces of the sintered body obtained by firing at 1370°C ± 20°C for 2 hours, and then baked at 800°C.
Silicone is adhered to the entire surface of the laminate thus prepared, and the silicone is polymerized by heat treatment in the range of 250 to 300°C for 4 to 6 hours, after which the heat-treated laminate is placed in a polypot with an inner diameter of 150 mm. The silicone on the silver electrode portions at both ends was removed by rolling at a rotational speed of 95 to 100 r.p.m. for 30 minutes.
Next, 1 to 2 μm of nickel plating was applied to the silver electrode portions at both ends from which the silicone had been removed, and then 1 to 2 μm of tin and lead alloy plating was applied thereon.
第1図はこのようにして得られた本発明の積層
セラミツクコンデンサを示し、図中1は磁器誘電
体層、2はパラジウム電極層、3は銀電極、4は
ニツケルメツキ層、5はスズと鉛の合金メツキ
層、6はシリコーン層である。 FIG. 1 shows the multilayer ceramic capacitor of the present invention thus obtained, in which 1 is a ceramic dielectric layer, 2 is a palladium electrode layer, 3 is a silver electrode, 4 is a nickel plating layer, and 5 is a tin and lead layer. 6 is an alloy plating layer, and 6 is a silicone layer.
また、第2図は本発明の方法に基づく積層セラ
ミツクコンデンサと、従来の方法に基づくシリコ
ーン処理のない積層セラミツクコンデンサ(シリ
コーン処理以外は本発明方法と同一である)の40
℃、相対湿度95%中での50V印加時の耐湿特性の
様子を示したものである。第2図でaは本発明品
の特性、bは従来品の特性である。この第2図か
ら明らかなように、本発明の方法に基づく積層セ
ラミツクコンデンサの耐湿特性は極めて安定して
いることが明白である。 Figure 2 shows a multilayer ceramic capacitor based on the method of the present invention and a multilayer ceramic capacitor based on the conventional method without silicone treatment (same as the method of the present invention except for the silicone treatment).
℃ and 95% relative humidity when 50V is applied. In FIG. 2, a shows the characteristics of the product of the present invention, and b shows the characteristics of the conventional product. As is clear from FIG. 2, it is clear that the moisture resistance of the multilayer ceramic capacitor based on the method of the present invention is extremely stable.
以上述べたように、本発明の方法によれば、メ
ツキ電極を設けた積層セラミツクコンデンサにあ
りがちな耐湿特性の不安定性といつた問題点を解
決し得た点で極めて有意義なものである。 As described above, the method of the present invention is extremely significant in that it is able to solve problems such as instability in moisture resistance, which are common in laminated ceramic capacitors provided with plated electrodes.
尚、上記実施例ではチタン酸バリウム,ジルコ
ン酸バリウム及びチタン酸カルシウムを主体とす
る磁器誘電体材料を使用したが、他の誘電体材料
に関しても適用可能なことは言うまでもないこと
である。また、両端面に銀電極をほどこした場合
について説明したが、銀―パラジウム合金電極で
もよいものである。 Incidentally, in the above embodiment, a porcelain dielectric material mainly composed of barium titanate, barium zirconate, and calcium titanate was used, but it goes without saying that other dielectric materials can also be used. Further, although the case where silver electrodes are provided on both end faces has been described, silver-palladium alloy electrodes may also be used.
第1図は本発明方法に基づく積層セラミツクコ
ンデンサの一部切欠斜視図、第2図は本発明方法
と従来方法に基づく積層セラミツクコンデンサの
耐湿特性の比較図である。
1……磁器誘電体層、2……電極層(パラジウ
ム電極層)、3……銀電極、4……ニツケルメツ
キ層、5……スズと鉛の合金メツキ層、6……シ
リコーン層。
FIG. 1 is a partially cutaway perspective view of a multilayer ceramic capacitor based on the method of the present invention, and FIG. 2 is a comparison diagram of the moisture resistance characteristics of multilayer ceramic capacitors based on the method of the present invention and the conventional method. 1... Porcelain dielectric layer, 2... Electrode layer (palladium electrode layer), 3... Silver electrode, 4... Nickel plating layer, 5... Tin and lead alloy plating layer, 6... Silicone layer.
Claims (1)
有する、磁器誘電体層及びクシ形状に電極層が交
互に積層されてなる積層体の全面にシリコーンを
付着すると共にこのシリコーンの付着した積層体
を熱処理してシリコーンを重合させ、その後両端
部の銀電極部に付着したシリコーンを除去し、つ
いでニツケルメツキを両端部の銀電極部にほどこ
し、このニツケルメツキ処理部分にスズと鉛の合
金メツキをほどこすようにした積層セラミツクコ
ンデンサの製造方法。1. Silicone is adhered to the entire surface of a laminate consisting of a porcelain dielectric layer and a comb-shaped electrode layer that are alternately laminated with silver or silver-palladium alloy electrodes on both ends, and the laminate with this silicone attached is heat treated. After that, the silicone adhering to the silver electrodes at both ends is removed, and then nickel plating is applied to the silver electrodes at both ends, and tin and lead alloy plating is applied to the nickel plating treated parts. A manufacturing method for multilayer ceramic capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56165187A JPS5866321A (en) | 1981-10-15 | 1981-10-15 | Method of producing laminated ceramic condenser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56165187A JPS5866321A (en) | 1981-10-15 | 1981-10-15 | Method of producing laminated ceramic condenser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5866321A JPS5866321A (en) | 1983-04-20 |
| JPH0113206B2 true JPH0113206B2 (en) | 1989-03-03 |
Family
ID=15807487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56165187A Granted JPS5866321A (en) | 1981-10-15 | 1981-10-15 | Method of producing laminated ceramic condenser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5866321A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59202618A (en) * | 1983-04-30 | 1984-11-16 | 松下電器産業株式会社 | Method of producing laminated ceramic condenser |
| JPH0727803B2 (en) * | 1985-11-20 | 1995-03-29 | 松下電器産業株式会社 | Electrode treatment method for laminated chip varistor |
| JPH01241809A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Laminated ceramic chip parts |
-
1981
- 1981-10-15 JP JP56165187A patent/JPS5866321A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5866321A (en) | 1983-04-20 |
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