JPH01132143A - Manufacture of semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device with extremely high reliability.

Generally, a semiconductor substrate on which a transistor or the like is formed is usually sealed with a sealing body such as a ceramic package (including a method of sealing a ceramic package with glass), a ceramic package using a metal cap, or a plastic package. . Among these packages, the ceramic material of the ceramic package in particular contains uranium, thorium, etc. in a few ppm or less.

On the other hand, plastic packaging materials use fine particles such as alumina called filler, and the filler also contains the above-mentioned impurities.

These impurities are, for example, 16th proceeded
ingsof reliability physics
S (1978), p. 33, it is known that alpha rays are emitted and can cause malfunctions (referred to as soft errors) in dynamic memory circuits constructed within semiconductor pellets.

By the way, it has been found that soft errors caused by α rays also occur in various memory circuits described below.

First, a static type MOS as shown in Figure 1
This is the case for memory cell circuits. This cell circuit
As shown in the plan view of the figure, it is composed of a diffusion region (dotted line) formed in a semiconductor substrate 1 and a wiring layer formed on the surface of the semiconductor substrate 1. Note that FIG. 2 only shows the wiring layer of the power supply line VL and the word line WL, which are made of a diffusion region (dotted line) formed in the semiconductor substrate 1 and a polycrystalline silicon layer formed on the surface thereof. . The bit lines S and B and the ground line G in FIG. 1, which are omitted to complicate the drawing, are made of an aluminum layer and are connected to the surface of the semiconductor substrate 1 through an insulating layer so as to cross the power supply line VL and word line WL. formed on top.

Therefore, in the ρ semiconductor memory device shown in FIG. 2, which constitutes one cell circuit as shown in FIG. 1, the MOS transistor Q is turned off, while the MO8) transistor Q2 is turned on.
Assume that information of "l" is held. In such a state, the α rays emitted from the package are transmitted to the transistor Q1.
When the drain diffusion region D1 (connection point A in FIG. 1) is hit, a hole-electron pair is generated in the semiconductor substrate directly under this drain diffusion region D1. On the other hand, in this semiconductor memory device, the positive power supply voltage VDD is applied to the power supply line VL, and since the MOS transistor Q□ is off, the drain diffusion region has almost no power supply voltage VDD.
The potential level of DD is given.

Therefore, negative electrons are induced into this drain diffusion region. Therefore, the potential at the gate of the MOS transistor Q2 (connection point A in Figure 1) connected to this drain diffusion region decreases, and the potential at the gate of the MOS transistor Q (connection point B in Figure 1) decreases. It becomes lower than the potential.

As a result, MOS transistor Q is turned on, and MOS)
The transistor Q2 turns off and the information of w1'' is reversed to the information of @0''.

Similarly, even if this semiconductor memory device holds information of "0", it will be inverted to information of IIIN by being hit by α rays. That is, MOS transistor Q1 is on, while MOS transistor Q,
is off, α rays emitted from the package penetrate the drain diffusion region D2 of the transistor Q2 (connection point B in Fig. 1).
), (for the same reason as above, the potential of the gate (connection point B in FIG. 1) of the MOS transistor Q connected to the drain diffusion region D2 decreases,
Gate of MOS transistor Q2 (connection point A in Figure 1)
The potential will be lower than the potential of

As a result, MOS) transistor Q1 turns off, and MOS)
The transistor Q2 turns on, and the information of "on" is reversed to the information of "1".

Next is the case of a dynamic 16-bit NMOS memory circuit.

FIG. 3 shows part of the circuit. In the figure, a dummy cell DMC is used to compare the voltage level of a memory cell MC8°MC with a sense amplifier AMP.
On the other hand, it is used to compare the voltage levels of dummy cell DMC3; or memory cell MC, by sense amplifier AMP. Similarly, dummy cell DMC2 is memory cell Mc
49Mc.

The Oi voltage level is used for comparison by the sense amplifier AMP2, while the dummy cell DMC is used for comparing the voltage levels of the two MCs by the sense amplifier AMP2. Note that A D + and A D 2 indicate address circuits.

In a semiconductor device that constitutes such a memory circuit, it goes without saying that alpha rays emitted from the package may hit the memory cell or dummy cell portion, causing malfunctions.
It also occurs in MP, Nototo. Especially this sense amplifier AMP! .

It was observed that the soft errors occurring in AMP2 were extremely high compared to the soft errors occurring in the memory cell and dummy cell portions. The reason for this is 1.
This is thought to be because the area of one sense amplifier is considerably larger than that of one cell, and the data lines DL, DL are diffusion layers and have a high probability of being hit by α rays.

Next, a soft error that occurs when the sense amplifier of this memory circuit is hit by α rays emitted from the package will be explained using the voltage fluctuation characteristic diagram shown in FIG.

Assume that information "0" in memory cell MC in FIG. 3 is read out.

The MOS transistors Qs and Qa are turned on by a signal of a clock pulse φ. As a result, the data lines DL, DL, are at the VDD level, that is, "1".
Precharged to level. tl in FIG. 4 is the time when precharging starts. After precharging is completed, information is read. At the start of reading (+2), the word line WD of the dummy cell and the word line W2 of the memory cell
is selected, dummy cell DMC, MOS) transistor Q7 and memory cell MC1's MOS) transistor Q
8 turns on. At this time, the voltage levels of the data lines DL, DL2 fall as shown in FIG.

The capacitance value of capacitor C6 of tammy cell DMC is cell M
The capacitance value of the capacitor C2 is approximately 1/2 of the capacitance value of the capacitor C2. Therefore, immediately after +2, the data line DL
, decreases as shown by the solid line. On the other hand, the voltage level of data line DL2 decreases as shown by the dashed line.

When the MOS transistor Q, which amplifies the voltage level difference between the data lines DL and DL, is turned on by the clock pulse φ, that is, before the amplification start time t has elapsed, α is emitted from the package. If the line changes to the data line DL, the voltage level of the data lines DL and DL2 after tl when the amplification is started will be the same as the dotted line DL1 in FIG.
, the state is as shown in DL2. And time t4
Amplification is completed at this point.

However, at the time tXO shown in FIG.
When it comes to data line DL, for the same reason as in the case of the semiconductor memory device that constitutes the static type MOS memory cell circuit described above, the data line DL.

voltage level decreases. Then, at time t, the voltage levels of data lines DL and DL are reversed.

Therefore, the data line DL after the start of amplification (+3).

The voltage levels of DL and DL are as shown in DL and DL in FIG. Then, at the time t4 when the amplification is completed, the voltage levels of the data lines DL and DL2 are completely inverted.

Therefore, originally, the potential of data line DL is approximately at the VDD level, and MOS transistor Q+'.

is turned on, and the potential of data line DL2 is at ground level.
S) This is to turn off the transistor QII, but due to the influence of α rays, the potential of the data line DL becomes the ground level, and the potential of the data line DL becomes the VDD level, so it is a MOS)
Transistor Qto is turned off, and MOS transistor Q
n is turned on.

As a result, the information in memory cell MC is as if it were “1”.
”.

Such a problem is caused by the information “1” in the memory cell MC.
This also occurred when reading . In this case, information inversion occurred when the α ray was on the data line DL.

The above-mentioned sense amplifier is constructed in and on the semiconductor substrate 1 as shown in FIG.

In the figure, a gate electrode G made of polycrystalline silicon,
The source diffusion region S11 and the drain diffusion region Dll constitute a MOS transistor Qt+. and a gate electrode G made of polycrystalline silicon; 2. Source diffusion region S+2 and drain diffusion region 1. constitutes MOS transistor Q+2. Gate electrode G1. is the connection point J, and the drain diffusion region DI
Connected to 2. - On the other hand, the gate electrode G,2 has a drain diffusion region at the connection point J2. It is connected to the. It is connected to a drain diffusion region (not shown) of a MOS transistor Q. The second aluminum wiring layer 2 is connected to the source diffusion regions S11 and S12 at connection points J and J4. Note that the drain diffusion regions 1 and DI2 extend in the lateral direction to be used as data lines DL and DL2, respectively.

Furthermore, this is the case for bipolar memory cell circuits.

The bipolar memory cell circuit, as shown in Figure 6,
It consists of resistors R+, R2, diode DI-D2, and multi-emitter transistors Q+2+Q10. The common connection line of the diodes D, ID2, resistors R,, rL, is connected to the word line W+, and the transistor Q12'IQ
One emitter of each Cs is connected to a pit line B.
, , B, and the other emitter is connected to an information holding constant current source IST.

The above-mentioned bipolar memory cell circuit is known, and information retention is performed by the stable state of a bistable circuit, that is, a flip-flop circuit. That is, transistor Q
When a potential difference between the bases of +t + QCs occurs, positive feedback occurs due to the collector pace cross-coupling, and among the transistors Q and 2+ Q10, the one with the higher pace potential turns on, and the other transistor turns off, resulting in one It becomes stable.

In DC terms, this information retention ability is determined by the potential difference between the bases of transistor Q+t+Q10 in a stable state.

In terms of AC, the ease with which a flip-flop circuit can be reversed depends on the transistor's current amplification factor, high frequency gain bandwidth, pace resistance, parasitic capacitance, etc., and the resistance connected as a load to the collector of the transistor. (R1
, Re ) and the high frequency characteristics of the diode (D2.D, ).

In order to improve the information retention ability, it is sufficient to deteriorate the high frequency characteristics caused by these. However, in order to increase the speed of bipolar memory, it is necessary to improve these characteristics, and in ultra-high-speed bipolar memory, the information retention ability inevitably decreases as the speed increases.

In such Voibora memory, information inversion can be explained as follows.

In a semiconductor substrate that constitutes a bipolar memory circuit, when alpha rays emitted from a package that seals the substrate enter the substrate, pairs of holes and electrons are generated due to energy loss of the alpha rays during the incident path. These holes and electron bears are collected through the collector-paste region depletion layer and collector region-substrate depletion layer of the transistor, and generate noise current. In FIG. 6, when transistor Q+2 is on and transistor Q13 is off, in normal operation, the collector potential VC of transistor Q+3 is as shown by the solid line in FIG.
t has a higher potential relationship than the collector potential VCO of transistor Q+z. However, among the hole-electron pairs generated when α rays enter the substrate, those collected by the depletion layer between the collector and base regions become noise current ■. occurs. This noise current In is the parasitic capacitance C between the collector and pace region of the transistor Q+s.
It flows through TC2 and lowers the collector potential VCI of transistor QI3. For this reason, the flip-flop memory cell begins to perform an inversion operation, as shown by the dotted line and the dashed-dotted line in FIG. 7, and shifts to one stable state. Then, a complete information reversal occurs.

In this way, memory circuits that use charges to retain information malfunction due to alpha rays.

Therefore, the present invention uses polyimide resin or polyimide isoindolo quinazolinedione resin (hereinafter referred to as P
It is attenuated and absorbed by resin (hereinafter referred to as II resin).

Hence the damping material.

The resin coating film serving as the absorbent material is required to be thick enough to prevent α particles from passing through. In order to keep the device characteristics from changing, this thickness should be at least 1.
It is preferably 0 μm or more, and more preferably 30 μm or more. The ability to prevent the transmission of alpha rays is not limited to the resin coating film, but is an ability generally possessed by insulating films.

However, it is extremely difficult to deposit insulating films such as silicon dioxide, phosphorous glass, silicon nitride, and aluminum oxide, which have been conventionally used in semiconductor devices, on a semiconductor substrate to a thickness of 10 μm or more. That is, these insulating films formed by vapor phase growth have extremely high film stress, and cracks occur when the film is deposited to a thickness of several micrometers or more. Furthermore, with the sputtering method, it is possible to deposit with a relatively low crack generation rate, but the deposition rate is extremely low at several hundred v minutes, and it is practically impossible to deposit 10 μm or more. On the other hand, polyimide resin and PII
With resin, the film stress is extremely small at approximately 4Kpf/-.
In addition, the strain at break is about 30%, which is about an order of magnitude larger than that of the inorganic insulating film, so the thickness of the film is several tens of μm? It can be formed without any generation. On the other hand, some polymer resins have film-forming properties similar to those of the polyimide resin and PII resin films described above. Generally, the sealing process for ceramic packages is performed at a high temperature of around 450C.
Heat resistance that can withstand this temperature is required. The above-mentioned resins are examples of resins that satisfy this property.

As shown in the margin below, or an example in Figure 8, when thermogravimetric loss analysis is performed on various polymer resins, silicone resin 13
, epoxy resin 14, etc., start to lose weight from 200 to 250C, but polyimide resin 12 starts to lose weight from 500C. PII resin 11 has even better heat resistance, and the weight residual rate at 600C is about 70%, which is the best. In this way, polyimide resin or PII resin.

It has heat resistance to the above-mentioned high temperature process.

In addition, in PII resin or polyimide resin,
The content of impurities such as uranium and thorium, which are sources of alpha rays, is extremely small, ranging from 0.1 to several ppb (analysis of these impurities was performed by activation analysis). Therefore, P
II resin or polyimide resin blocks alpha rays emitted from ceramic packaging materials, and at the same time, the resin itself tends to be of very high purity (therefore, the amount of alpha rays it also generates is extremely small.On the other hand, In general, it can be said that organic polymer materials have a lower content of impurities than inorganic materials. However, as an example of organic polymer materials, in the case of polyethylene resin, the uranium content is 40 to 50 parts.
Organic polymer materials are not necessarily suitable for use with relatively large amounts of Pb and polyimide resins. Both PII resins and polyimide resins can be said to be excellent materials in terms of the content of impurities such as uranium and thorium. However, As mentioned above, PII resin is more preferable from the viewpoint of heat resistance.

In addition, here, polyimide resin refers to a polymer obtained by reacting aromatic diamine and aromatic tetracarboxylic dianhydride, and PII resin refers to a polymer obtained by reacting aromatic diamine, aromatic tetracarboxylic acid, and aromatic tetracarboxylic dianhydride. It refers to a polymer obtained by reacting with diaminocarbonamide, and all of them are well known.For PII resin, for example, Japanese Patent Publication No. 48-2956
The patent publication No. 2003-100007 describes the process in detail, including its manufacturing method.

Since the area forming part of the memory circuit formed within the semiconductor substrate is affected by alpha rays, the amount of resin coating film provided to prevent the intrusion of alpha rays is small (at least on that area). must exist.

Note that, if the semiconductor substrate has an insulating layer, an electrode, a wiring layer, etc., these are also included. The semiconductor device of the present invention is mainly constituted by a monolithic integrated circuit.

Ceramic encapsulation is a well-known technology in the semiconductor technology field.
Any conventionally used ceramic seal can be used. These ceramic packages include:
For example, they are called a cofired dip or a corfired dip. These ceramics usually have alumina ceramics as their main component, and glass, whose main component is lead glass, is used for adhesion between ceramics in the ceramic type.

Polyimide resin and PII resin have a small amount (about several ppm)
may contain alkaline impurities such as Na. In this case, by forming a resin film such as polyimide resin on the semiconductor substrate and applying high temperature heat treatment, the semiconductor substrate is formed! Since pinholes and the like exist in the insulating film provided on the surface of the thin semiconductor plate, the alkali impurities may enter through these areas and change the device characteristics. To prevent this, it is effective to form a glass film or a silicon nitride film with a high alkali ion blocking ability on the semiconductor substrate and to interpose it between the film and the polyimide resin.

Hereinafter, the effects of the present invention will be explained in more detail according to Examples.

Example 1 This will be explained according to FIG. 9. A film having a thickness of 4 to 40 nm is formed on the P-type silicon semiconductor substrate 21 constituting the memory circuit as described above.
A PII resin film 23 of 37 μm was formed.

PII resin is applied onto the wafer by spin-on method,
A heat treatment of 200C for 1 hour was applied to semi-cure, and the bonding pad portion 22 was opened by photoetching with a hydrazine aqueous solution. After that, 350C1 hour, 450C1
It was completely cured by heat treatment for 0 minutes. The heat treatment is preferably carried out in nitrogen or an inert gas. PIQ (registered trademark of Hitachi Chemical Co., Ltd.) was used as the I'II resin.

In each of the following examples, PIQ is also used as the PII resin. Further, this base body was sealed in a ceramic package (Sardip) as shown in FIG.

In addition, in FIG. 9, 20 is an N-type diffusion region constituting a part of the memory circuit, and 21' is an insulating film 1, for example, Sr.
The Ox film 211 is a wiring conductor layer, and 24 is a bonding wire connected to an external connection lead. Further, in FIG. 1O, 25 indicates an external connection lead.

26 is molten glass to which the ceramic 27 is bonded in a sealed manner.

Example 2 PII resin is formed on a semiconductor substrate by another method as follows.

As shown in FIG. 11, a P-type silicon semiconductor substrate 61 is die-bonded to a predetermined position of the package, a bonding wire 62 is bonded by wire bonding for external connection, and then a PII resin 63 is bonded. death.

Heat treatment was performed at 200C for 1 hour, 350O for 1 hour, and 450C for 10 minutes. The PII resin film thickness is about 40 to 70 μm. It is desirable to extend the insulating film 61' over the scribe region 64.

Example 3 As mentioned above, polyimide resin contains a small amount (about several ppm)
may contain alkaline impurities such as Na. At this time, if a polyimide resin film is formed on the semiconductor substrate and subjected to high-temperature heat treatment, pinholes may be present in the insulating film 71' as shown in FIG. If a portion 76 or the like is generated due to misalignment of the mask 71', impurity ions may enter from these portions and change the device characteristics. Therefore, it is effective to form a phosphorous glass or silicon nitride film having a high ability to block alkali ions on the semiconductor substrate and interpose it between the film and the polyimide resin. That is, as shown in FIG. 12, a phosphorus glass 73 is formed on a silicon semiconductor substrate 71 by vapor phase growth, and a polyimide film 74 is further formed thereon. Ring glass is 3 mo
- Phosphorus concentration from e% to 12moA%, film thickness 0.3μm
The thickness is preferably about 1.5 μm. In other words, the ability of the phosphorus glass membrane to block alkali ions depends on the phosphorus concentration;
Effects appear from oA% or higher. On the other hand, as the phosphorus concentration increases, the hygroscopicity increases, so when it exceeds 12 moA%, defects such as AA wiring corrosion begin to occur. The film thickness of the phosphor glass needs to be at least 0.3 μm or more in order to almost completely cover the semiconductor substrate, and 1 μm or more is required as a range that does not cause cracks due to the tensile stress of the phosphor glass itself.
．． The thickness is preferably 5 μm or less.

The polyimide resin film 74 was formed by the same method as in Example 1. There is no ring glass like this.

If there are pinholes or mask misalignment 76 in the insulating film 71' as described above, a polyimide resin film 74 is formed and a high temperature heat treatment of 4001:' or higher is applied.
A decrease in yield of about 5 to 40% was observed.

However, in this example, it was confirmed that the yield was not reduced due to the formation of the polyimide resin film (in addition, no malfunctions occurred due to α-ray irradiation).

A similar effect is confirmed when a silicon nitride film is used instead of the phosphorus glass 730. The silicon nitride film is formed by sputtering method, plasma CVD (Plasma Enh.
anced Chemical VaporDep
The plasma CVD method is preferably used. Film thickness is 0.2'''3
A range of μm is desirable. The thickness of the silicon nitride film is still required to be 0.2 μm or more in order to almost completely cover the semiconductor substrate, and the upper limit is about 3 μm, which is a range in which plasma etching of the silicon nitride film described below can be easily performed. desirable. This silicon nitride film is made of, for example, CF4
The opening can be opened by plasma etching.

In FIG. 12, 75 indicates a bonding wire.

In this example, PI was used instead of polyimide resin.
It is clear that the same effect as the present invention can be achieved by using I resins or by forming these resins by the potting method.

Example 4 In this example, a polyimide resin or PII resin film 81 having openings 82 shown in FIG. 13 was pressure-bonded onto a silicon semiconductor wafer. Openings 82 correspond to bonding pad areas and scribe areas of the semiconductor body. This film is 50-500 μm thick.

Also in this example, no soft error occurred due to α-ray irradiation. The effect of the present invention on ceramic sealing is also clear. Note that this semiconductor wafer has film 8.
After coating 1, it is guised into pellets.

Example 5 The area of the silicon wafer other than the element area (area where soft errors occur due to α-ray irradiation) was covered with a printing mesh screen, and a prepolymer solution of PIQ (concentration 19.5%, viscosity Approximately 10.0OOcp)
After roller coating, it was baked at 200t11' for 60 minutes and then at 350C for 60 minutes to form a 50 μm thick PIQ film only on the element region. Also in this example, no soft errors occurred due to α-ray irradiation. Furthermore, the effect on the soft error occurrence rate after ceramic sealing is clear.

Example 6 After a pellet (semiconductor device) was mounted on a package pedestal, the pellet was covered with an uncured or semi-cured film of polyimide resin or PII resin, and then betatized at 350C for 30 minutes. An uncured film was obtained as follows. That is, a polyimide prepolymer solution (for example, Toshisha Trenyce: #3000)
Alternatively, a PIQ prepolymer was coated on a flat substrate (eg, a glass plate) and then baked at 100 C to substantially volatilize the solvent and form an uncured film with a thickness of 30 to 50 μm. Next, they used a sharp cutter to cut the pieces into pieces that matched the dimensions of the pellets, peeled them off the board, and placed them over the pellets that made up the memory circuit. Similarly, when baked at 200C, the thickness is still 30℃.
A semi-cured film of ~50 μm is obtained. Place the uncured and semi-cured film over the pellets for 35 minutes.
After baking at 0C for 30 minutes, these films adhered well to the pellets and functioned well as a protective film.

Furthermore, the semiconductor memory device manufactured in this manner did not suffer from any soft errors due to alpha ray irradiation.

As a modification of this method, instead of the polyimide resin or PII resin film piece, a Si piece of the same shape is adhered onto the active element area with a polyimide resin or PII4T4 resin prepolymer, and this effect is also lost. do not have. At this time, it is desirable to oxidize the surface of the Si piece by thermal oxidation. Furthermore, polyimide or P
If, for example, a heat-treated product of an A2 chelate compound is formed on the surface of the thermally oxidized film before adhesion with the II resin prepolymer, adhesion will be improved.

According to the present invention, the following specific effects were obtained.

Figure 14 shows a 16-bit NMOS dynamic RAM (llandomAcc) using 5V as the power supply voltage VDD.
2 is a graph showing the number of knot errors caused by alpha rays in a semiconductor substrate constituting a circuit, with and without a PIIi oil film coated on the substrate.

In this figure, the vertical axis shows the number of soft errors per minute, and the horizontal axis shows the α-ray source with an energy of 5 MeV (
Americium) strength.

The unit of α-ray source intensity is microchielly (μCi).

As shown in the figure, a considerable amount of soft errors occur in the semiconductor substrate E which is not coated with any PII resin film. On the other hand, α
The source strength is only 102 μCi, but it is 20 μCi.
In the semiconductor substrate F coated with the μ PII resin film, the number of soft errors was reduced to about 1/10' compared to the semiconductor substrate E. Furthermore, in the semiconductor substrate G coated with a 50 μm PII resin film, the thickness decreased to about 1/10′ or less compared to the semiconductor substrate E.

Incidentally, the maximum energy of α rays is 8.8 MeV, and the energy for creating hole-electron pairs within a silicon semiconductor substrate is 3.7 eV. Therefore, the number of electrons created by one α ray is approximately 2.4×10′. Therefore, M.O.S.

Regardless of whether it is bipolar, dynamic type, or static type, the information in the memory circuit “1” is stored by less than this charge.
Semiconductor memory devices that form "0" or "0" will definitely be affected.

Therefore, it is extremely effective to apply the present invention to such a semiconductor memory device.

The present invention is a CCD (Charge-Coupled-D
The present invention can also be applied to semiconductor memory devices constituting memory circuits such as (devices). In the case of a CCD, no diffusion region is provided, and a portion of the semiconductor substrate surface itself constitutes a portion of the memory circuit.

Note that the sealing body applied to the present invention is not limited to the one made of the above-mentioned ceramic material (it also includes one made of an insulating material such as a metal material or glass).

In addition, Ladder Polymer (LadderP) is used as a heat-resistant resin.
olymer), such as phenyl ladder silicon (
Phenyl Ladder S, 1licon) is used.

[Brief explanation of the drawing]

Fig. 1 is a static type MOS memory cell circuit diagram, Fig. 2 is a plan view of a semiconductor substrate forming part of the cell circuit in Fig. 1, and Fig. 3 is a partial circuit diagram of a pit dynamic type NMOS memory circuit at 16. , Fig. 4 is a voltage level change characteristic diagram in the memory circuit of Fig. 3, Fig. 5 is a plan view of the semiconductor substrate that constitutes the sense amplifier part of Fig. 3, Fig. 6 is a bipolar memory cell circuit diagram, and Fig. 7 6 is a voltage (potential) level change characteristic diagram in the cell circuit, FIG. 8 is a graph showing thermogravimetric reduction curves of various polymer resins, and FIG. 9 is a graph showing a polymer resin film in an embodiment of the present invention. FIG. 10 is a cross-sectional view of a semiconductor memory device formed by ceramic-sealing the semiconductor substrate, and FIG. 11 is a cross-sectional view of a semiconductor substrate formed by a potting method in an embodiment of the present invention. FIG. 12 is a cross-sectional view of a semiconductor substrate in which a phosphorus glass or silicon nitride film and a resin film are formed on a semiconductor substrate in one embodiment of the present invention, and FIG. 13 is a cross-sectional diagram in one embodiment of the present invention. FIG. 14, which is a plan view of a semiconductor substrate with a resin film pressed onto the semiconductor substrate, is a graph showing the number of soft errors caused by alpha rays when the semiconductor substrate is coated with a PII resin film and when it is not coated with a PII resin film. 1.21.61.71...Semiconductor substrate constituting a memory circuit, 11.23.63...PII resin. 12.74... Polyimide resin film, 20... Diffusion region, 27... Ceramic, 73... Phosphorus glass film,
76... Mask misalignment portion, 81... Resin film, 82... Opening portion. Agent: Patent attorney Katsuo Ogawa Fig. 1 Fig. 2 Fig. 3 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 3: ja; (μ6 gradient

Claims (1)

[Claims] 1. A step of forming a region constituting a memory circuit in a semiconductor region on one main surface of a semiconductor wafer, a step of forming a metal wiring layer having a bonding pad portion on the region constituting the memory circuit, and a step of forming the memory circuit. A semiconductor characterized by comprising the step of forming a coating film of a resin material selected from the group consisting of polyimide resin and polyimide-isoindolo-quinazolinedione resin on one main surface of a semiconductor wafer on which a constituent region is formed. A method for manufacturing a storage device.