JPH01135552U - - Google Patents

Info

Publication number
JPH01135552U
JPH01135552U JP3090888U JP3090888U JPH01135552U JP H01135552 U JPH01135552 U JP H01135552U JP 3090888 U JP3090888 U JP 3090888U JP 3090888 U JP3090888 U JP 3090888U JP H01135552 U JPH01135552 U JP H01135552U
Authority
JP
Japan
Prior art keywords
computer system
personal computer
microprocessor
under test
communication port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3090888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3090888U priority Critical patent/JPH01135552U/ja
Publication of JPH01135552U publication Critical patent/JPH01135552U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、この考案のプログラムトレーサをカ
バレージトレーサに適用した一実施例のブロツク
図である。 １…プログラムアドレストレーサ、２…通信ポ
ート、３…パソコンシステム、４…被測定装置、
５…アダプター、６…インタフエース、７…ダイ
ナミツクトレースコントローラ、８…スタテツク
トレートコントローラ、９…トレース範囲コント
ローラ、１０…マイクロプロセツサ、１１…メモ
リリード／ライトコントローラ、１２…ダイナミ
ツクトレースメモリ、１３…スタテツクトレース
メモリ。 FIG. 1 is a block diagram of an embodiment in which the program tracer of this invention is applied to a coverage tracer. 1...Program address tracer, 2...Communication port, 3...PC system, 4...Device under test,
5...Adapter, 6...Interface, 7...Dynamic trace controller, 8...Static rate controller, 9...Trace range controller, 10...Microprocessor, 11...Memory read/write controller, 12...Dynamic trace memory, 13...State trace memory.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パーソナルコンピユータシステムとの通信ポー
トを有し、マイクロプロセツサを有する被測定装
置に接続されて、前記パーソナルコンピユータシ
ステムに制御され、前記被測定装置から採取した
前記マイクロプロセツサが実行するプログラムに
ついてのトレースデータを前記通信ポートを介し
て前記パーソナルコンピユータシステムに転送し
、前記パーソナルコンピユータシステム側におい
て前記マイクロプロセツサが実行するプログラム
の評価処理をすることを特徴とするプログラムア
ドレストレーサ。 A trace of a program executed by the microprocessor that has a communication port with a personal computer system, is connected to a device under test having a microprocessor, is controlled by the personal computer system, and is collected from the device under test. A program address tracer characterized in that data is transferred to the personal computer system via the communication port, and a program executed by the microprocessor is evaluated on the personal computer system side.
JP3090888U 1988-03-08 1988-03-08 Pending JPH01135552U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3090888U JPH01135552U (en) 1988-03-08 1988-03-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3090888U JPH01135552U (en) 1988-03-08 1988-03-08

Publications (1)

Publication Number Publication Date
JPH01135552U true JPH01135552U (en) 1989-09-18

Family

ID=31256372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3090888U Pending JPH01135552U (en) 1988-03-08 1988-03-08

Country Status (1)

Country Link
JP (1) JPH01135552U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607554A (en) * 1983-06-27 1985-01-16 Nippon Telegr & Teleph Corp <Ntt> Measuring system for performance of computer system
JPS62221043A (en) * 1986-03-20 1987-09-29 Nec Corp Monitor circuit for logical unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607554A (en) * 1983-06-27 1985-01-16 Nippon Telegr & Teleph Corp <Ntt> Measuring system for performance of computer system
JPS62221043A (en) * 1986-03-20 1987-09-29 Nec Corp Monitor circuit for logical unit

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