JPH0184152U - - Google Patents

Description

[Brief explanation of the drawing]

Figures 1 to 3 relate to an embodiment of this invention,
Figure 1 is a block diagram showing the memory device, Figure 2 is a circuit diagram of the memory protect circuit in Figure 1,
FIG. 3 is a diagram showing the relationship between memory space and write control data, and FIG. 4 is a block diagram showing a conventional memory device. In the figure, 1 is a control device main body, 2 is a memory element control circuit, 3 is a memory element, 4 is a memory protect circuit, 6 is a data bus, 7 is an address bus, 8 is a signal, 9 is a signal, and 10 is a data bus transceiver. , 11 is an address bus buffer, and 12 is a memory element. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A control device main body that instructs an address to be written into a memory address space via a data bus, a memory element control circuit that selects a memory element corresponding to a certain memory address space, and a write from the control device main body that corresponds to the memory space. A memory device that includes a memory protection circuit that reads control data and generates a write signal.