JPH01137660A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01137660A
JPH01137660A JP62295241A JP29524187A JPH01137660A JP H01137660 A JPH01137660 A JP H01137660A JP 62295241 A JP62295241 A JP 62295241A JP 29524187 A JP29524187 A JP 29524187A JP H01137660 A JPH01137660 A JP H01137660A
Authority
JP
Japan
Prior art keywords
lead frame
lead
semiconductor device
leads
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62295241A
Other languages
Japanese (ja)
Inventor
Toshihiro Tsuboi
敏宏 坪井
Masahiko Nishiuma
雅彦 西馬
Atsushi Honda
厚 本多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP62295241A priority Critical patent/JPH01137660A/en
Publication of JPH01137660A publication Critical patent/JPH01137660A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To connect a plurality of rows of leads in parallel to surface mount the leads of a plurality of lead frames on a mounting substrate, and to mount the leads in high density by providing a lead frame structure in which the leads of the plurality of lead frames are superposed through insulating adhesives. CONSTITUTION:A lead frame structure 4 in which a second lead frame 2 is superposed by adhering with an insulating adhesive 3, such as polyimide resin on a first lead frame 1 is employed as a normal lead frame. Then, the lead frames 1, 2 are connected in two rows, and can be surface mounted on a mounting substrate 8. Thus, the number of pins of one package is increased, thereby mounting them in high density.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に間し゛、特に低コストで多ピン
化に好適なパッケージ構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to a package structure suitable for low cost and multi-pin implementation.

〔従来の技術〕[Conventional technology]

従来のデュアル・インライン・パッケージ（以下、ＤＴ
Ｐという）、クオツド・フラン１〜・パッケージ（以下
、ＱＦＰという）等の面付半導体装置は、そのリードを
一列に配列接続して実装基板に実装されている。Conventional dual inline package (hereinafter referred to as DT)
A surface-mounted semiconductor device such as a QFP package (hereinafter referred to as QFP) is mounted on a mounting board with its leads arranged and connected in a line.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、本発明者の検討によれば、前記従来の面
付半導体装置では、リードフレームの多ピン化への点に
ついて配慮がされておらず、ＱＦＰのピン数がリードフ
レームのエツチング精度のみに依存するため、ＱＦＰの
実装密度向上の点で問題があった。However, according to the inventor's study, in the conventional surface-mounted semiconductor device, no consideration was given to increasing the number of pins on the lead frame, and the number of pins of the QFP depends only on the etching precision of the lead frame. Therefore, there was a problem in improving the packaging density of QFP.

本発明の目的は、ＱＦＰパッケージでの多ビン化への対
応及び実装密度向上を図ることが可能な技術を提供する
ことにある。An object of the present invention is to provide a technology that can cope with the increase in the number of bins in a QFP package and improve the packaging density.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔問題点を解決するための手段〕[Means for solving problems]

本願において開示される発明のうち１代表的なものの概
要を説明すれば、下記のとおりである。An overview of one typical invention disclosed in this application is as follows.

すなわち、樹脂封止型半導体装置において、複数枚のリ
ードフレームのインナーリードをそれぞれ絶縁性接着剤
を介在させて重ねたリードフレーム構造体を備えたもの
である。That is, the resin-sealed semiconductor device includes a lead frame structure in which inner leads of a plurality of lead frames are stacked with an insulating adhesive interposed therebetween.

〔作　用〕[For production]

前記した手段によれば、複数枚のリードフレームのイン
ナーリードをそれぞれ絶縁性接着剤を介在させて重ねた
リードフレーム構造体を備えたことにより、実装基板に
リードを並列に複数列接続して面付実装することができ
るので、１つのパッケージのビン数を増加することが可
能となり、高密度実装を図ることができる。According to the above-mentioned means, by providing a lead frame structure in which the inner leads of a plurality of lead frames are stacked one on top of the other with an insulating adhesive interposed between them, multiple rows of leads are connected in parallel to a mounting board and a surface can be formed. Since the number of bins in one package can be increased, high-density packaging can be achieved.

以下、本発明の一実施例を図面を用いて説明する。An embodiment of the present invention will be described below with reference to the drawings.

なお、全回において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔実施例〕〔Example〕

第１図は、本発明をＤＩＰ型半導体装置に適用した一実
施例の外観構成を説明するための斜視図、第２図は、第
１図に示す■−■切断線で切った断面図。FIG. 1 is a perspective view for explaining the external configuration of an embodiment in which the present invention is applied to a DIP type semiconductor device, and FIG. 2 is a sectional view taken along the line 1--2 shown in FIG.

第３図は、第１図に示すＤＩＰ型半導体装置の樹脂封止
する前段の工程における概略構成を示す平面図、 第４図は、本発明のリードフレームの他の実施例の概略
構成を示す平面図、 第５図は、第１図に示す実装基板に設けられているパッ
ドのレイアウトを示す斜視図である。3 is a plan view showing a schematic structure of the DIP type semiconductor device shown in FIG. 1 in a step before resin sealing, and FIG. 4 is a plan view showing a schematic structure of another embodiment of the lead frame of the present invention. 5 is a perspective view showing the layout of pads provided on the mounting board shown in FIG. 1. FIG.

第１図及び第２図に示すように、本実施例のＤＩＰ型半
導体装置は、第１リードフレーム１の上に第２リードフ
レーム２をポリイミド系樹脂等の絶縁性接着剤３で接着
して重ね合せたリードフレーム構造体４を通常のリード
フレームとして使用したものである。リードフレームｌ
のタブｌＣにペレット５を接着剤でペレット付けする。As shown in FIGS. 1 and 2, the DIP type semiconductor device of this embodiment has a second lead frame 2 bonded onto a first lead frame 1 with an insulating adhesive 3 such as polyimide resin. The stacked lead frame structure 4 is used as a normal lead frame. lead frame l
Attach pellet 5 to tab IC with adhesive.

ペレット５のポンディングパッドと、第１リードフレー
ム１のインナーリードＩＡ及び第２リードフレーム２の
インナーリード２Ａとを各々ボンディングワイヤ６（ボ
ール・ウェッジボンディング）により電気的に接続する
。それ全体をレンジ等の封止用樹脂７によりモールド封
止したものである。The bonding pad of the pellet 5 is electrically connected to the inner leads IA of the first lead frame 1 and the inner leads 2A of the second lead frame 2 by bonding wires 6 (ball wedge bonding). The whole is mold-sealed with a sealing resin 7 such as a microwave oven.

前記第１リードフレーム１の上に第２リードフレーム２
をポリイミド系樹脂等の絶縁性接着剤３で接着して重ね
合せたリードフレーム構造体４は。A second lead frame 2 is placed on the first lead frame 1.
The lead frame structure 4 is made by bonding and overlapping the following with an insulating adhesive 3 such as polyimide resin.

第３図に示すように、下段の第１リードフレーム１のイ
ンナーリードＩＡを上段の第２リードフレーム２のイン
ナーリード２Ａより長くしである。As shown in FIG. 3, the inner leads IA of the first lead frame 1 in the lower stage are longer than the inner leads 2A of the second lead frame 2 in the upper stage.

また、第１リードフレーム１の上に第２リードフレーム
２をポリイミド系樹脂等の絶縁性接着剤３で接着して重
ね合せたリードフレーム構造体４は、第４図に示すよう
に、下段の第１リードフレームｌのインナーリードＩＡ
と上段の第２リードフレーム２のインナーリード２Ａと
をずらして交互に配置してもよい。Further, as shown in FIG. 4, a lead frame structure 4 in which a second lead frame 2 is bonded and stacked on top of the first lead frame 1 with an insulating adhesive 3 such as polyimide resin is constructed as shown in FIG. Inner lead IA of first lead frame l
and the inner leads 2A of the second lead frame 2 in the upper stage may be staggered and arranged alternately.

また１本実施例のＤＩＰ型半導体装置は、第１図に示す
ように、実装基板８の上に実装される。Further, the DIP type semiconductor device of this embodiment is mounted on a mounting board 8, as shown in FIG.

すなわち、実装基板８にはパッド（端子）８Ａ。That is, the mounting board 8 has pads (terminals) 8A.

８Ｂが並列に配設され、それぞれパッド８Ａには第１リ
ードフレーム１のアウターリードＩＢが接続され、パッ
ド８Ｂには第２リードフレーム２のアウターリード２Ｂ
が接続される。8B are arranged in parallel, the outer lead IB of the first lead frame 1 is connected to the pad 8A, and the outer lead 2B of the second lead frame 2 is connected to the pad 8B.
is connected.

以上の説明かられかるように１本実施例によれば、２枚
のリードフレーム１及び２のインナーリードＩＡ及び２
Ａをそれぞれポリイミド系樹脂等の絶縁性接着剤３を介
在させて重ねたリードフレーム構造体４を備えたことに
より、実装基板８にリードフレーム１及び２を２列に接
続して面付実装することができるので、１つのパッケー
ジのピン数を増加することができ、高密度実装を図るこ
とができる。As can be seen from the above description, according to this embodiment, the inner leads IA and 2 of the two lead frames 1 and 2
By providing a lead frame structure 4 in which A is stacked with an insulating adhesive 3 such as polyimide resin interposed therebetween, lead frames 1 and 2 are connected in two rows to a mounting board 8 for surface mounting. Therefore, the number of pins in one package can be increased, and high-density packaging can be achieved.

以上、本発明を実施例にもとずき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変形可能であること
はいうまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

例えば、前記リードフレーム構造体４は、前記実施例に
限定されるものではなく、その機能を果すものであれば
どのようなものでもよい。For example, the lead frame structure 4 is not limited to the embodiment described above, and may be of any type as long as it fulfills its function.

また、前記実施例はＤＩＰ型半導体装置に本発明を適用
したが１本発明はこれ以外の面付実装半導体装置にも適
用できることは勿論である。Furthermore, although the present invention was applied to a DIP type semiconductor device in the above embodiment, it goes without saying that the present invention can also be applied to other surface-mounted semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

すなわち、複数枚のリードフレームのインナーリードを
それぞれ絶縁性接着剤を介在させて重ねたリード構造体
を備えたことにより、実装基板にリードを並列に複数列
接続して実装することができるので、１つのパッケージ
のピン数を増加することが可能となり、高密度実装を図
ることができる。In other words, by providing a lead structure in which the inner leads of a plurality of lead frames are stacked one on top of the other with an insulating adhesive interposed between them, it is possible to connect and mount multiple rows of leads in parallel on a mounting board. It becomes possible to increase the number of pins in one package, and high-density packaging can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は５本発明をＤＩＰ型半導体装置に適用した一実
施例の外Ｈ構成を説明するための斜視図、第２図は、第
１図に示す■−■切断線で切った断面図、 第３図は、第１図に示すＤＩＰ型半導体装置の樹脂封止
する前段の工程における概略構成を示す平面図、 第４図は、本発明のリードフレームの他の実施例の概略
構成を示す平面図。 第５図は、第１図に示す実装基板に設けられているパッ
ドのレイアウトを示す斜視図である。 図中、１・・・第１リードフレーム、ＩＡ、２Ａ・・・
インナーリード、ＩＢ、２Ｂ・・・アウターリード、２
・・・第２リードフレーム、３・・・絶縁性接着剤、４
・・・リードフレーム構造体、６・・・ボンディングワ
イヤ、５・・・ペレット、７・・・対土用樹脂、８・・
・実装基板、８Ａ、８Ｂ・・・パッド（端子）である。 第１図 第２図FIG. 1 is a perspective view for explaining the outer H configuration of an embodiment in which the present invention is applied to a DIP type semiconductor device, and FIG. 2 is a cross-sectional view taken along the cutting line ``--'' shown in FIG. 1. , FIG. 3 is a plan view showing a schematic structure of the DIP type semiconductor device shown in FIG. 1 in the step before resin sealing, and FIG. 4 is a schematic structure of another embodiment of the lead frame of the present invention. A plan view shown. FIG. 5 is a perspective view showing the layout of pads provided on the mounting board shown in FIG. 1. In the figure, 1...first lead frame, IA, 2A...
Inner lead, IB, 2B...outer lead, 2
...Second lead frame, 3...Insulating adhesive, 4
... Lead frame structure, 6... Bonding wire, 5... Pellet, 7... Resin for soil, 8...
- Mounting board, 8A, 8B... Pads (terminals). Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 １、半導体装置において、複数枚のリードフレームのイ
ンナーリードをそれぞれ絶縁性接着剤を介在させて重ね
たリードフレーム構造体を備えたことを特徴とする半導
体装置。 ２、前記リードフレーム構造は、下段のリードフレーム
のインナーリードが上段のリードフレームのインナーリ
ードより長いことを特徴とする特許請求の範囲第１項に
記載の半導体装置。 ３、前記リードフレーム構造体は、２枚のリードフレー
ムを絶縁性接着剤を介在させて重ねたものであって、下
段のリードフレームのインナーリードと上段のリードフ
レームのインナーリードとをずらして交互に配置したこ
とを特徴とする特許請求の範囲第１項又は第２項に記載
の半導体装置。[Scope of Claims] 1. A semiconductor device comprising a lead frame structure in which inner leads of a plurality of lead frames are stacked with an insulating adhesive interposed therebetween. 2. The semiconductor device according to claim 1, wherein in the lead frame structure, the inner leads of the lower lead frame are longer than the inner leads of the upper lead frame. 3. The lead frame structure is made by stacking two lead frames with an insulating adhesive interposed between them, and the inner leads of the lower lead frame and the inner leads of the upper lead frame are shifted and alternated. The semiconductor device according to claim 1 or 2, characterized in that the semiconductor device is arranged in.
JP62295241A 1987-11-25 1987-11-25 Semiconductor device Pending JPH01137660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62295241A JPH01137660A (en) 1987-11-25 1987-11-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62295241A JPH01137660A (en) 1987-11-25 1987-11-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01137660A true JPH01137660A (en) 1989-05-30

Family

ID=17818042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62295241A Pending JPH01137660A (en) 1987-11-25 1987-11-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01137660A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990016079A3 (en) * 1989-06-09 1991-02-07 Jaesup N Lee Low impedance packaging
US5014113A (en) * 1989-12-27 1991-05-07 Motorola, Inc. Multiple layer lead frame
FR2664097A1 (en) * 1990-06-28 1992-01-03 Sgs Thomson Microelectronics Integrated circuit housing and its method of manufacture
US5438021A (en) * 1992-04-17 1995-08-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a multiple-chip semiconductor device with different leadframes
US7133169B2 (en) 1996-11-05 2006-11-07 Yoshiki Tsuchiyama Apparatus equipped with removable scanner unit
US7379218B1 (en) 1996-11-05 2008-05-27 Fujitsu Limited Apparatus equipped with removable scanner unit
JP2009016843A (en) * 2007-07-09 2009-01-22 Samsung Techwin Co Ltd Lead frame structure and semiconductor package including the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990016079A3 (en) * 1989-06-09 1991-02-07 Jaesup N Lee Low impedance packaging
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5014113A (en) * 1989-12-27 1991-05-07 Motorola, Inc. Multiple layer lead frame
FR2664097A1 (en) * 1990-06-28 1992-01-03 Sgs Thomson Microelectronics Integrated circuit housing and its method of manufacture
US5438021A (en) * 1992-04-17 1995-08-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a multiple-chip semiconductor device with different leadframes
US7133169B2 (en) 1996-11-05 2006-11-07 Yoshiki Tsuchiyama Apparatus equipped with removable scanner unit
US7379218B1 (en) 1996-11-05 2008-05-27 Fujitsu Limited Apparatus equipped with removable scanner unit
JP2009016843A (en) * 2007-07-09 2009-01-22 Samsung Techwin Co Ltd Lead frame structure and semiconductor package including the same
US7952175B2 (en) * 2007-07-09 2011-05-31 Samsung Techwin Co., Ltd. Lead frame, semiconductor package including the lead frame and method of forming the lead frame

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