JPH01139452U - - Google Patents

Info

Publication number
JPH01139452U
JPH01139452U JP1988035140U JP3514088U JPH01139452U JP H01139452 U JPH01139452 U JP H01139452U JP 1988035140 U JP1988035140 U JP 1988035140U JP 3514088 U JP3514088 U JP 3514088U JP H01139452 U JPH01139452 U JP H01139452U
Authority
JP
Japan
Prior art keywords
thick
integrated circuit
multilayer substrate
hybrid integrated
film multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988035140U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988035140U priority Critical patent/JPH01139452U/ja
Publication of JPH01139452U publication Critical patent/JPH01139452U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図及び第２図は本考案の実施例に係るハイ
ブリツドＩＣの夫々断面図及び底面図、第３図は
同ハイブリツドＩＣを検査するソケツトの一例を
示す断面図、第４図は本考案の他の実施例に係る
ハイブリツドＩＣの断面図、第５図は従来のハイ
ブリツドＩＣの断面図である。 １，１１；厚膜多層基板、２，１２；内部導体
配線、３，１３；スルーホール、４，１４；ＩＣ
ペレツト、５，１５；ボンデイングワイヤ、６，
１８；リード端子、１６；ハイブリツドＩＣ本体
、１７；ケース、１９；外部電極、２０；ハイブ
リツドＩＣ、２３；ソケツト、２４；リード端子
用測定ピン、２５；外部電極用測定ピン。

Claims (1)

    【実用新案登録請求の範囲】
  1. 厚膜多層基板と、この厚膜多層基板上に構成さ
    れた混成集積回路本体と、前記厚膜多層基板の側
    面に配置され前記混成集積回路本体の一部の端子
    を外部へ導くリード端子と、前記厚膜多層基板の
    裏面に配置され前記混成集積回路本体の他の端子
    を外部へ導く外部電極とを具備したことを特徴と
    する混成集積回路。
JP1988035140U 1988-03-16 1988-03-16 Pending JPH01139452U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988035140U JPH01139452U (ja) 1988-03-16 1988-03-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988035140U JPH01139452U (ja) 1988-03-16 1988-03-16

Publications (1)

Publication Number Publication Date
JPH01139452U true JPH01139452U (ja) 1989-09-22

Family

ID=31261795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988035140U Pending JPH01139452U (ja) 1988-03-16 1988-03-16

Country Status (1)

Country Link
JP (1) JPH01139452U (ja)

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