JPH01140212A - Low voltage mos reference voltage circuit - Google Patents
Low voltage mos reference voltage circuitInfo
- Publication number
- JPH01140212A JPH01140212A JP62295997A JP29599787A JPH01140212A JP H01140212 A JPH01140212 A JP H01140212A JP 62295997 A JP62295997 A JP 62295997A JP 29599787 A JP29599787 A JP 29599787A JP H01140212 A JPH01140212 A JP H01140212A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- reference voltage
- circuit
- input terminal
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 230000007423 decrease Effects 0.000 description 2
- 101000738757 Homo sapiens Phosphatidylglycerophosphatase and protein-tyrosine phosphatase 1 Proteins 0.000 description 1
- 102100037408 Phosphatidylglycerophosphatase and protein-tyrosine phosphatase 1 Human genes 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、１．０ Ｖ以下の低電圧の電源で正確な基準
電圧を発生させることができるＭＯＳ基準電圧回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS reference voltage circuit that can generate an accurate reference voltage with a low voltage power supply of 1.0 V or less.
この種の基準電圧回路として、第３図に示す差動増幅回
路がある。この回路は、差動接続されるＭＯＳＮチャン
ネルのＦＥＴＮＩ、Ｎ２と、それら両ＦＥＴの負荷とし
て機能するカレントミラー接続のＭＯＳＰチャンネルの
ＦＥＴＰＩ、Ｒ２と、その差動回路の出力回路を構成す
るＰチャンネルのＦＥＴＰ３とで構成されている。差動
接続の一方のＦＥＴＮＩのゲート（非反転入力端子）は
接地され、他方のＦＥＴＮ２のゲート（反転入力端子）
には出力端子ｌに得られる出力信号が帰還されている。As this type of reference voltage circuit, there is a differential amplifier circuit shown in FIG. This circuit consists of a differentially connected MOSN channel FET NI, N2, a current mirror connected MOSP channel FET PI, R2 that functions as a load for both FETs, and a P channel that constitutes the output circuit of the differential circuit. It is composed of FETP3. The gate of one FETNI (non-inverting input terminal) of the differential connection is grounded, and the gate of the other FETN2 (inverting input terminal)
The output signal obtained at the output terminal l is fed back.
Ｒ１は出力抵抗、Ｃ１は位相補正用コンデンサ、■は定
電流源である。なお、第４図はこの回路の等価回路であ
り、２は差動増幅回路である。R1 is an output resistance, C1 is a phase correction capacitor, and ■ is a constant current source. Incidentally, FIG. 4 shows an equivalent circuit of this circuit, and 2 is a differential amplifier circuit.
この回路では、出力端子ｌに得られる基準電圧ＶＲは、
Ｖ Ｒ＝ Ｖ Ｔ Ｈｓｔ Ｖ Ｔ ＨＮＩ
−（１）となる。ＶＴＨ，４，はＦＥＴＮ２１
７）閾値電圧、ＶＴＨＮＩはＦＥＴＮＩの閾値電圧であ
る。In this circuit, the reference voltage VR obtained at the output terminal l is VR=V T Hst V T HNI
−(1). VTH, 4, is FETN21
7) Threshold Voltage, VTHNI is the threshold voltage of FETNI.
ところが、この回路では、温度係数を良くするために、
両開値電圧の差、つまり基準電圧ＶＲを１．０ Ｖ以上
とする必要があり、このため電源電圧を１．Ｏｖ以上と
する必要があった。また、ＦＥＴの閾値電圧の差を基準
電圧として利用しているので、低い閾値のＦＥＴＮＩを
デプレッシッン型のＦＥＴ（ゲート電圧を零にしてもド
レイン電流が流れる。）とする必要があり、そのため同
一サイズ（ゲート幅と長さが同じ）であっても、Ｇｍに
大きな差が生じるので、それをサイズ調整して補正しな
ければならなかった。However, in this circuit, in order to improve the temperature coefficient,
It is necessary to set the difference between the two open voltages, that is, the reference voltage VR, to 1.0 V or more, and for this reason, the power supply voltage should be set to 1.0 V or more. It needed to be Ov or higher. In addition, since the difference in threshold voltage of FETs is used as a reference voltage, it is necessary to use a depressing type FET (drain current flows even when the gate voltage is zero) for the FETNI with a low threshold value, so (Even if the gate width and length are the same), there is a large difference in Gm, so this had to be corrected by adjusting the size.
本発明はこのような点に鑑みてなされたものであり、得
られる基準電圧を１．Ｏｖよりも充分低くしながらも、
温度補償を良好にした低電圧ＭＯＳ基準電圧回路を提供
することである。The present invention has been made in view of these points, and the obtained reference voltage is set to 1. Although it is sufficiently lower than Ov,
An object of the present invention is to provide a low voltage MOS reference voltage circuit with good temperature compensation.
〔問題点を解決するための手段〕
このために本発明は、非反転入力端子を接地し反転入力
端子に出力信号を帰還させた差動増幅回路でなり、該回
路の差動接続される２個のＭＯＳＦＥＴの上記非反転入
力端子側の閾値電圧を上記反転入力端子側の閾値電圧よ
りも高くして、両閾値電圧差に基づいた基準電圧を得る
ＭＯＳ基準電圧回路において、
上記出力信号の得られる端子に温度係数大きな抵抗を接
続すると共に該抵抗と接地間に温度係数の小さな抵抗を
接続し、該両抵抗の共通接続部の電圧を上記反転入力端
子に帰還させて構成した。[Means for solving the problem] For this purpose, the present invention comprises a differential amplifier circuit in which a non-inverting input terminal is grounded and an output signal is fed back to an inverting input terminal, and two differentially connected terminals of the circuit are provided. In the MOS reference voltage circuit, the threshold voltage on the non-inverting input terminal side of each MOSFET is made higher than the threshold voltage on the inverting input terminal side, and a reference voltage is obtained based on the difference between both threshold voltages. A resistor with a large temperature coefficient is connected to the terminal connected to the resistor, and a resistor with a small temperature coefficient is connected between the resistor and the ground, and the voltage at the common connection between the two resistors is fed back to the inverting input terminal.
以下、本発明の実施例について説明する。第一図はその
一実施例の基準電圧回路を示す図、第２図はその等価回
路図である。第２図に示したものと同一のものには同一
の符号を附した。本実施例では、出力端子ｌと接地間に
抵抗Ｒ２と抵抗Ｒ３を直列接続し、両抵抗Ｒ２、Ｒ３の
共通接続点から差動接続の一方のＦＥＴＮ２のゲート（
反転入力゛端子）に帰還させている。また、抵抗Ｒ２は
抵抗Ｒ３よりも温度係数が大きなものを使用している。Examples of the present invention will be described below. FIG. 1 is a diagram showing a reference voltage circuit of one embodiment, and FIG. 2 is an equivalent circuit diagram thereof. Components that are the same as those shown in FIG. 2 are given the same reference numerals. In this embodiment, a resistor R2 and a resistor R3 are connected in series between the output terminal l and the ground, and the gate of one of the differentially connected FETN2 (
It is fed back to the inverting input (terminal). Further, the resistor R2 has a larger temperature coefficient than the resistor R3.
この回路では、出力端子１に得られる基準電圧ＶＲを抵
抗Ｒ２とＲ３で分割した電圧が負帰還されるので、その
基準電圧ＶＲは、
となる。即ち、ＦＥＴＮＩとＦＥＴＮ２の閾値電圧の差
を充分低く設定しても、抵抗Ｒ２とＲ３の比を適宜設定
することにより所望の基準電圧を得ることができる。よ
って、閾値電圧の差を例えば０．３ ｖ程度に設定する
ことができ、電源電圧も１．０Ｖ以下にすることができ
る。In this circuit, the voltage obtained by dividing the reference voltage VR obtained at the output terminal 1 by the resistors R2 and R3 is negatively fed back, so the reference voltage VR is as follows. That is, even if the difference between the threshold voltages of FETNI and FETN2 is set sufficiently low, a desired reference voltage can be obtained by appropriately setting the ratio of resistors R2 and R3. Therefore, the difference in threshold voltage can be set to, for example, about 0.3 V, and the power supply voltage can also be set to 1.0 V or less.
また、このように閾値電圧の差が小さくて済むので、Ｇ
ｍの差もさほど大きくはならず、ＦＥＴサイズの補正量
も少なくて済む。よって、回路の差動バランスが向上し
基準電圧の対電源電圧依存性も少なくなる。In addition, since the difference in threshold voltage can be small in this way, G
The difference in m is not so large, and the amount of correction of the FET size can be small. Therefore, the differential balance of the circuit is improved and the dependence of the reference voltage on the power supply voltage is reduced.
また、閾値電圧の差が小さくなるので、温度変化の影響
を受けやすくなるが、抵抗Ｒ２とＲ３の温度係数ＴＲ２
、ＴＲ３を、ＴＲ２＞ＴＲ３としているので、温度の低
下に伴って低下する閾値電圧差に対して、抵抗Ｒ３より
も抵抗Ｒ２の値が相対的に増大するので、温度補償が行
われ、式（２）の値に大きな変化は生じない。Also, since the difference in threshold voltage becomes smaller, it becomes more susceptible to temperature changes, but the temperature coefficient TR2 of resistors R2 and R3
, TR3 is set as TR2>TR3, so the value of resistor R2 increases relatively more than that of resistor R3 with respect to the threshold voltage difference that decreases as the temperature decreases, so temperature compensation is performed, and the formula ( There is no significant change in the value of 2).
また、この回路では、両開値の差を大きくする必要がな
いので、両ＦＥＴＮＩ、Ｎ２共にエンハンスメント型の
ものを使用することができる。Further, in this circuit, since there is no need to increase the difference between the opening values, both FETs NI and N2 can be of the enhancement type.
以上のように本発明によれば、低い値の基準電圧を得る
ことができ、またその場合の温度補償も充分に行うこと
ができるという特徴がある。As described above, the present invention is characterized in that it is possible to obtain a reference voltage of a low value, and in that case, it is also possible to perform sufficient temperature compensation.
第１図は本発明の一実施例のＭＯＳ基準電圧回路の回路
図、第２図はその等価回路図、第３図は従来の同様な基
準電圧回路の回路図、第４図はその等価回路図である。
ｌ・・・出力端子、Ｒ２・・・温度係数の大きい抵抗、
Ｒ３・・・温度係数の小さい抵抗。
代理人 弁理士 長 尾 常 明
第１図
第２図
第３図Figure 1 is a circuit diagram of a MOS reference voltage circuit according to an embodiment of the present invention, Figure 2 is its equivalent circuit diagram, Figure 3 is a circuit diagram of a similar conventional reference voltage circuit, and Figure 4 is its equivalent circuit. It is a diagram. l...output terminal, R2...resistance with large temperature coefficient,
R3...Resistance with small temperature coefficient. Agent: Patent Attorney Tsuneaki NagaoFigure 1Figure 2Figure 3
Claims (1)
号を帰還させた差動増幅回路でなり、該回路の差動接続
される２個のＭＯＳＦＥＴの上記非反転入力端子側の閾
値電圧を上記反転入力端子側の閾値電圧よりも高くして
、両閾値電圧差に基づいた基準電圧を得るＭＯＳ基準電
圧回路において、上記出力信号の得られる端子に温度係
数大きな抵抗を接続すると共に該抵抗と接地間に温度係
数の小さな抵抗を接続し、該両抵抗の共通接続部の電圧
を上記反転入力端子に帰還させたことを特徴とするＭＯ
Ｓ基準電圧回路。(1) It is a differential amplifier circuit in which the non-inverting input terminal is grounded and the output signal is fed back to the inverting input terminal, and the threshold voltage on the non-inverting input terminal side of the two differentially connected MOSFETs of the circuit is is higher than the threshold voltage on the inverting input terminal side to obtain a reference voltage based on the difference between both threshold voltages, a resistor with a large temperature coefficient is connected to the terminal from which the output signal is obtained, and the resistor An MO characterized in that a resistor with a small temperature coefficient is connected between the resistor and ground, and the voltage at a common connection between the two resistors is fed back to the inverting input terminal.
S reference voltage circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62295997A JPH01140212A (en) | 1987-11-26 | 1987-11-26 | Low voltage mos reference voltage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62295997A JPH01140212A (en) | 1987-11-26 | 1987-11-26 | Low voltage mos reference voltage circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01140212A true JPH01140212A (en) | 1989-06-01 |
Family
ID=17827797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62295997A Pending JPH01140212A (en) | 1987-11-26 | 1987-11-26 | Low voltage mos reference voltage circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01140212A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0580866A (en) * | 1991-09-20 | 1993-04-02 | Nec Corp | Reference voltage circuit |
| US5892390A (en) * | 1995-07-11 | 1999-04-06 | Mitsubishi Denki Kabushiki Kaisha | Internal power supply circuit with low power consumption |
| JP2007109034A (en) * | 2005-10-14 | 2007-04-26 | New Japan Radio Co Ltd | Constant current circuit |
| JP2007537539A (en) * | 2004-05-12 | 2007-12-20 | フリースケール セミコンダクター インコーポレイテッド | Voltage adjustment implementation circuit |
-
1987
- 1987-11-26 JP JP62295997A patent/JPH01140212A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0580866A (en) * | 1991-09-20 | 1993-04-02 | Nec Corp | Reference voltage circuit |
| US5892390A (en) * | 1995-07-11 | 1999-04-06 | Mitsubishi Denki Kabushiki Kaisha | Internal power supply circuit with low power consumption |
| JP2007537539A (en) * | 2004-05-12 | 2007-12-20 | フリースケール セミコンダクター インコーポレイテッド | Voltage adjustment implementation circuit |
| JP2007109034A (en) * | 2005-10-14 | 2007-04-26 | New Japan Radio Co Ltd | Constant current circuit |
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