JPH01140232A - Microprogram control system - Google Patents

Abstract

PURPOSE:To realize a microsequence signal whose degree of freedom is high by determining the return address of a register when an index address in an address register coincides with the address of a program language being executed. CONSTITUTION:The respective addresses of the index address and the return address are respectively read out of a control storage 2 by the specific microinstruction of a microprogram in a control storage 1, these are respectively stored into address registers 7 and 8 and next, an address coincidence is detected by a comparing circuit 9. The microprogram intends to use one part of another microprogram as a sub-routine, branches unconditionally, the return address is supplied to the microprogram by the address held by the register 8 at the time of detecting the coincidence and a return to a microprogram sequence to a main routine is attained. As this result, the microprogram steals the logic of one part of another microprogram.

Description

TECHNICAL FIELD The present invention relates to a microprogram control system, and more particularly to a microprogram sequence control system that allows any microprogram sequence to be stolen and executed as if it were a subroutine.

One of the conventional software programming methods is the subroutine method. This takes a functional part common to several programs and makes it a subroutine, and each program routine (this is called a main routine as opposed to a subroutine) calls this subroutine as necessary to use its functions. Although it is a method, it is also used in microprograms.

Conventionally, in microprogram-controlled data processing devices,
The subroutine method is realized by setting the return address from the subroutine in a register in advance during the main routine, and placing a microinstruction at the end of the subroutine that instructs to jump to the return address stored in this register. It is supposed to be done.

In the implementation method using the conventional technology described above, it is necessary to prepare a microinstruction at the exit of the subroutine to instruct a return to the main routine, so I would like to use a part of routine A, which has already been designed, as a subroutine. In this case, there is a drawback that this routine A cannot be used unless it is designed as a subroutine, or only a part of a designed subroutine cannot be used as a subroutine.

Purpose of the Invention Therefore, the present invention was made to solve the above-mentioned drawbacks of the conventional method, and its purpose is to make it possible to freely use a part of an existing microprogram routine without any changes. In this way, it is an object of the present invention to provide a microprogram control method capable of realizing microsequence stealing in an open manner and with a high degree of freedom.

Structure of the Invention According to the present invention, a first control memory that stores a microprogram, a second control memory that stores an index address and a return address on the first control memory, and a second control memory that stores an index address and a return address on the first control memory;
a register for storing the read index address and return address, respectively, from the second control memory according to a specific microinstruction read from the control memory; Comparing means for comparing the indexed address stored in the register with the address of the microprogram word being executed is provided, and when a match is detected by the comparing means, the address of the microprogram word to be executed next is determined. A microprogram control method is obtained, characterized in that the return address is stored in the register.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in the figure, this embodiment has a first control memory 1 that stores a microprogram indicating the execution procedure of machine instructions, a second &1jtlB memory 2 that stores a plurality of sets of addresses, and a first control memory 1.
A microinstruction register 3 and a microaddress register 4, which respectively store the microinstruction word and its address read from the microinstruction register 3. A microinstruction decoder 5 that analyzes the microinstructions in the microinstruction register 3. Micro address generation circuit 61 index address register 7, return address register 8. Comparison circuit 9. It consists of a flip-flop 10° and gate 11 and a selection circuit 12.

Each microinstruction word of the microprogram is read from the first control memory 1 and held in the microinstruction register 3;
The decoder 5 analyzes and controls the execution unit (not shown), and at the same time the micro-address generating circuit 6 generates the address of the micro-instruction word to be executed next, and the address of the micro-instruction word to be executed next is sent to the first control memory via the selection circuit 12. A machine instruction is executed by sequentially repeating the operation of supplying a read address to 1.

Here, a specific field of the microinstruction word held by the microinstruction register 3 is supplied to the second control memory 2 as a read address via a signal line 31. Now, when a specific microinstruction (this is named "SRS" microinstruction and this expression is used for convenience below) is decoded by the decoder 5, the second control memory at the address indicated in the specific field of the microinstruction word is decoded by the decoder 5. The contents of 2 are stored in the address register 7 and the return address register 8, and at the same time, the 7-rip-off block 10 is set to logic "1", the AND gate 11 is opened, and a comparison match signal, which will be described later, is activated. .

Comparison circuit 9 compares the addresses held in micro address register 4 and index address register 7, respectively.
If the two match, a comparison match signal is output to the signal line 91 to reset the flip 70 knob 10.

If a match is detected in the comparison circuit when the flip 70 knob 10 is set to logic "1", the output of the AND circuit 11 becomes the logic value "1", and as a result, the selection circuit 12 selects the micro address generation circuit 6. The return of the microprogram sequence to the main routine is achieved by supplying the first control memory 1 with a return address held in the return address register 8 instead of the address generated by the 7-lip-flop 10. Therefore, the microprogram sequence is not changed by the above coincidence detection until the "S RS" microinstruction appears next.

Next, the effect of the microprogram sequence 1 of the microprogram control method shown in FIG. 1 will be explained with reference to FIG. Each block in FIG. 2 represents a microprogram word, and the lines connecting each block represent the flow of execution of each program word, in other words, the microprogram sequence. Each microprogram word consists of multiple microinstructions that can be processed in parallel, such as step C
The above-mentioned "'SR8" microinstruction is described as one of them. Also, the fact that a plurality of lines are coming out of one block indicates that a conditional branch microinstruction is written in that block, and that the flow of the line is to proceed to one of the lines depending on the branch condition.

Now, when microprogram 1 reaches step C, S
RS "The microinstruction reads out the address of step P as the index address and the address of step D' as the return address from the second control memory 2, and sets these as the first
The address is stored in the index address register 7 and return address register 8 shown in the figure, respectively, and an address match check is started.

Microprogram 1 unconditionally branches to step R with the intention of using part of microprogram 2 as a subroutine, and steps R->S-+T-→Q→R
→U→■→P, and since an address match occurs at step P, it is possible to return to step D of the microphone [1 program 1] using the address held in the return address register 8.

In the end, A→B−+C→R→S→T→Q→R→U→v−+
The steps P-+D-+E→F are followed, and microprogram 1 can steal part of the logic of microprogram 2.

Note that when an address match occurs in step P and the process returns to step D, the flip-flop 10 is reset.
Micro program 2 after finishing micro program 1
Even if executed from the beginning, an address match will not occur in step P and a jump to step D will not occur.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a microphone [second address storing the index address and return address of one program] is provided.
At the start point of the index check, the desired index address and return address are retrieved and stored in a register to perform the index check, and branch to the desired return address when the index addresses match. By,
This method has the effect of eliminating the closedness that was characteristic of conventional subroutine configuration methods and realizing an open microsequence steal with a high degree of freedom. Furthermore, since a part of the existing microprogram routine can be freely used without making any equivalent changes, i.11
It is also effective in reducing the 111 memory capacity ω and improving the efficiency of development work.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a 70-ja-1 microprogram used in the embodiment of the present invention.
・It is a figure showing an example. Explanation of symbols of main parts 1...First control memory 2...Second control memory 7...Identification address register 8...
Return address register 9...Address comparison circuit 12...Address selection circuit

Claims (1)

[Claims] a first control memory storing a microprogram; a second control memory storing an index address and a return address on the first control memory; and a specific microinstruction read from the first control memory. means for reading an index address and a return address from the second control memory by means of a register; a register for storing the read index address and return address, respectively; and an index address stored in the register; and a comparison means for comparing the address of the microprogram word being executed, and when a match is detected by the comparison means, the address of the microprogram word to be executed next is the return address stored in the register. A microprogram control method characterized by: