JPH01140302A - I/o module for programmable controller - Google Patents

Abstract

PURPOSE:To smoothly operate an internal logic circuit by enabling an input/ output circuit to be switched to an input circuit and an output circuit by a means to switch the input/output circuit, and inputting the switching state of the circuit to a host logic circuit. CONSTITUTION:A gate control circuit 9 which switches plural input/output circuits 6,... which perform input and output between the outside to the input circuits or the output circuits by receiving the setting of a switch 8 and also, controls the transfer of data between an internal bus 4 and respective part, and a status input circuit 10 which sends the switching state of the input/output circuit 6 to a CPU1 are provided. Therefore, it is possible to combine the input/ output circuit freely, and to report the switching state of the circuit to the host logic circuit. In such a way, the host logic circuit can discriminate the setting state of the gate circuit easily, and performs its operation smoothly.

Description

[Detailed Description of the Invention] A. Industrial Field of Application The present invention is capable of freely switching any input/output circuit from an output circuit to an input circuit so that the internal logic circuit operates smoothly. It concerns the I10 module of the programmable controller.

B1 Overview of the Invention The present invention is a programmable controller I10 monoyl that performs input/output with the outside according to operation sequences and functions programmed by the user. A means for switching the gate circuit to a human horn circuit or an output circuit, and a means for reporting the switching state by the switching means to an upper logic circuit, so that the upper logic circuit can easily determine the setting state of the gate circuit. This allows input/output circuits to be freely combined and constructed, and the upper logic circuit can operate smoothly in response to the combination.

C1 Prior Art Conventionally, programmable controllers have been known that allow a user to program arbitrary operating sequences and functions at hand in order to control a controlled object. The programmable controller is
Generally, it is equipped with an I10 module that performs input/output to and from a controlled object. A conventional I10 module has an output module and an input module, each of which has a different internal logic circuit configuration.

Problems to be Solved by the D0 Invention However, in the I10 module of the programmable controller according to the above-mentioned conventional technology, the input module and the output module have different circuit configurations. It was extremely difficult to freely set the output circuit.

The present invention was devised to solve the above-mentioned problems, and it is possible to configure input/output circuits by freely combining them, and to operate smoothly in accordance with higher-level logic circuits or their combinations. The purpose is to provide 10 modules of programmable controllers.

Means for Solving the E1 Problems The programmable computer of the present invention achieves the above objects.
The configuration of the I10 module of the controller includes: a gate circuit that can be switched to both an input circuit and an output circuit; a means for switching the gate circuit to either an input circuit or an output circuit according to settings; and a means for transmitting the switching state by the switching means to the upper logic circuit. It is characterized by having a means for reporting.

F. Effect The present invention is equipped with a gate circuit that can be switched between an input circuit and an output circuit according to a setting, thereby making it possible to freely combine input and output circuits, and reporting the above switching state to a higher-level logic circuit. This enables the higher-level logic circuit to easily determine the setting state of the gate circuit and to perform its operation smoothly.

G. EXAMPLES Hereinafter, examples of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, a processor (hereinafter referred to as CPU) is used as the upper logic circuit.
110 bus 2 is used to indicate the I10 module connected to the CPU1 through the 110 bus 2 of the CPU1. This I10 module is connected to the I10 bus 2 by an internal bus 4 formed via a receiver 3.

The I10 module includes a register 5 that receives and receives output data from the CPUI from the internal bus 4, and a plurality of input/output circuits (Ilo, to I10n) that perform output to the outside.6.・・・
, an input buffer 7 that sends manual data input from the outside to the CPUI via the internal bus 4, and an input buffer 7 that switches each input/output circuit 6 to an input circuit or an output circuit according to the setting of a switch 8, and connects the internal bus 4. It consists of a gate control circuit 9 that controls data transfer between each part, a status input circuit IO that sends the switching status of the input/output circuit 6 to the CPU 1, and the like.

The gate control circuit 9 is connected to the internal bus 4,
In response to instructions from the CPU, a write signal WR for the register 5, a read signal RD for the input buffer 7, and a read signal GS for the status input circuit 10 are created, and the input/output circuit 6 is changed to an output circuit depending on the setting state of the switch 8. Output gate signal GW, ~G to operate as
Wn and input gate signals GR+ to GRn for operating as an input circuit are sent to the input/output circuit 6. Also,
The setting state of the switch 8 is sent as a status from the gate control circuit 9 to the status input circuit IO.

The register 5 is connected to each input/output circuit 6 (Ilo, ~l10n)
It is configured to be able to store output data for each corresponding address, is connected to the internal bus 4, and writes the output data at that time to the above address designated by the CPU 1 with a signal W.
Write by R.

The input circuit 6 includes a 3-state buffer 61 for output and a 3-state buffer 62 for input, and the output side of the 3-state buffer 61 and the input side of the 3-state buffer 62 have the same bit numbers. is connected to the connector 63. The input side of the three-state buffer 61 for output is connected to the output of the register 5 at the corresponding address. The output side of the 3-state buffer 62 for input is connected to the same bit numbers of other input/output circuits 6 and then to the input buffer 7 . The gate input of the 3-state buffer 761 receives output gate signals GW, ~GW.

is connected, and human-powered gate signals GR, -GWn are input to the human-powered gates of the 3-state buffer 62.

When each of the buffers 61 and 62 receives these gate signals, it is possible to output to the output side according to the signal on the input side, and when there is no gate signal, the output side becomes a floating state, and the other buffer circuits does not affect input/output. The input/output circuit 6 further includes either an input circuit 64 or an output circuit 64' for directly performing input/output with the outside. This input circuit 64 or output circuit 64' has a connector 65 that fits into the aforementioned connector 63, and is preferably configured to be detachable depending on the setting of the switch 8.

The operation of the embodiment configured as above will be described.

First, in the output operation, start from the upper cput! Book on 10 bus 2! Internal bus 4 via receiver 3 of 10 modules
The output data is written to the corresponding address in the register 5 through the write signal WR of the gate control circuit 9. The switch 8 is Ilo,, l10x,
- It is for setting whether the input/output circuit 6 of , Ilo, is an input circuit or an output circuit, for example, ■10. When the output circuit 6 of is set as an output circuit, the gate control circuit 9 opens the 3-state buffer 61 with the output gate signal GR, and closes the 3-state buffer 62 with the input gate signal GR.
The input/output circuit 6 of No. 1 operates as an output circuit. Also, ■
10. When the input/output circuit 6 is set as an input circuit, the gate control circuit 9 closes the 3-state buffer 61 with the output gate signal GWt, and opens the 3-state buffer 62 with the manual gate signal GR. in,
Ilo.

The input/output circuit 6 operates as an input circuit. Therefore, the output data mentioned above needs to be written to the address of the output circuit set by the switch 8.

Next, in the manual operation, when input data of a corresponding address is requested from the I10 bus 2, the gate control circuit 9 generates input gate signals GR, , G of that address.
By outputting only one signal R,,..., GRl to open the 3-state buffer 62 for one input, and then opening the input buffer 7 with the read signal RD, the input on the I10 bus 2 is Send data. In this case as well, the CPU
needs to issue a request for input data to the address of the input circuit set by the switch 8.

In the status input operation, the status input circuit IO indicates the setting state of the switch 8, that is, the input/output status of the I10 module (input/output circuit t10+, l10f).

..., whether l10n is an input circuit or an output circuit) is read out by the receiver 3. 11
0 bus 2 to the upper CPUUI, thereby
PU1 writes data to the corresponding address, and
enable loading.

In addition, in the above embodiment, the 3-state buffer 61.6
2 is an example of a gate circuit, switch 8, gate control circuit 9 is an example of means for switching the gate circuit to an input circuit or an output circuit, and status input circuit 10 is an example of means for reporting the switching state to the upper logic circuit. It is. These are not limited to the above-mentioned embodiments, but can be applied in various ways according to the spirit thereof, and can be implemented in various ways.

I] Effects of the Invention As is clear from the above explanation, according to the I10 module of the programmable controller of the present invention, the means for switching the input/output circuit can be used to switch between the input circuit and the output circuit, and the switching state can be changed. Since the information can be input to a higher-level logic circuit such as a CPU, the higher-level logic circuit can easily determine the setting status of the input/output circuit, and the internal logic circuit can operate smoothly. Therefore, the entire programmable controller can be operated extremely smoothly with simple switching operations, and input/output circuits can be freely combined.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. ! ...CPU, 9...Gate control circuit, I
O...Status input circuit, 61.62...3 state buffer.

Claims (1)

[Scope of Claims] A gate circuit that can be switched to both an input circuit and an output circuit, means for switching the gate circuit to an input circuit or an output circuit according to settings, and reporting a switching state by the switching means to a higher-order logic circuit. An I/O module of a programmable controller, comprising means.