JPH01143145U - - Google Patents

Info

Publication number
JPH01143145U
JPH01143145U JP4013088U JP4013088U JPH01143145U JP H01143145 U JPH01143145 U JP H01143145U JP 4013088 U JP4013088 U JP 4013088U JP 4013088 U JP4013088 U JP 4013088U JP H01143145 U JPH01143145 U JP H01143145U
Authority
JP
Japan
Prior art keywords
flat
adhesive surface
film
cream solder
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4013088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4013088U priority Critical patent/JPH01143145U/ja
Publication of JPH01143145U publication Critical patent/JPH01143145U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の分解斜視図、第2
図から第9図までは同実施例の使用によるフラツ
トIC基板の製造方法を示す図、そのうち、第2
図はプリント基板の平面図、第3図は同プリント
基板上に同実施例の透明なフイルム基板をあてた
平面図、第4図は本実施例の前記透明なフイルム
基板をとり除いた図、第5図はフラツトICを示
す平面図、第6図は同フラツトICの側面説明図
、第7図はプリント基板上にフラツトICを載置
した平面図、第8図は半田付けの方法を示す図、
第9図は本考案のフラツトIC基板製造用フイル
ムを治具として使用して製造したフラツトIC基
板の完成平面図である。 1…プリント基板、2…プリント配線、3…透
明なフイルム基板、3a…粘着面、4…剥離用フ
イルム、5…クリーム半田、6…フラツトIC、
7…フラツトICのピン。
Fig. 1 is an exploded perspective view of one embodiment of the present invention;
Figures 9 to 9 are diagrams showing a method of manufacturing a flat IC board using the same embodiment.
The figure is a plan view of the printed circuit board, FIG. 3 is a plan view of the same printed circuit board with the transparent film substrate of the same embodiment applied, and FIG. 4 is a view of the present embodiment with the transparent film substrate removed. Fig. 5 is a plan view showing the flat IC, Fig. 6 is an explanatory side view of the flat IC, Fig. 7 is a plan view of the flat IC mounted on a printed circuit board, and Fig. 8 shows the soldering method. figure,
FIG. 9 is a plan view of a completed flat IC board manufactured using the film for manufacturing flat IC boards of the present invention as a jig. 1... Printed circuit board, 2... Printed wiring, 3... Transparent film board, 3a... Adhesive surface, 4... Peeling film, 5... Cream solder, 6... Flat IC,
7...Flat IC pin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のプリント配線されたプリント基板上にフ
ラツトICの複数のピンを半田付けするためのク
リーム半田を一定の形状に転写塗布可能なフラツ
トIC基板製造用フイルムであつて、粘着面を有
するフイルム基板の粘着面上に前記一定の形状に
クリーム半田を配設粘着し、そのクリーム半田を
配設粘着した前記フイルム基板の粘着面上に剥離
用フイルムを粘着被覆してなる、フラツトIC基
板製造用フイルム。
A film for manufacturing a flat IC board that can be used to transfer and apply cream solder to a fixed shape for soldering multiple pins of a flat IC onto a printed circuit board with multiple printed wirings, and is a film substrate that has an adhesive surface. A film for producing a flat IC board, which comprises adhesively coating cream solder in the fixed shape on the adhesive surface of the film substrate, and adhesively covering the adhesive surface of the film substrate with the cream solder on the adhesive surface with a release film.
JP4013088U 1988-03-26 1988-03-26 Pending JPH01143145U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4013088U JPH01143145U (en) 1988-03-26 1988-03-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4013088U JPH01143145U (en) 1988-03-26 1988-03-26

Publications (1)

Publication Number Publication Date
JPH01143145U true JPH01143145U (en) 1989-10-02

Family

ID=31266606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4013088U Pending JPH01143145U (en) 1988-03-26 1988-03-26

Country Status (1)

Country Link
JP (1) JPH01143145U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191495A (en) * 1982-04-30 1983-11-08 ソニー株式会社 Method of attaching flux and solder to board with projection

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191495A (en) * 1982-04-30 1983-11-08 ソニー株式会社 Method of attaching flux and solder to board with projection

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