JPH01144148A - Bus controller - Google Patents

Abstract

PURPOSE:To avoid the data errors due to the invalid transfer data by detecting the foul activation of the mask information for a bus controller where the mask information showing the validity of data is transferred in addition to the data transferred via plural stages. CONSTITUTION:A decoder 1001 serves as a 1st detecting means which detects the discontinuous active state of the mask information based on the combination of active and inactive states of the mask bits in one stage. The flag means 1002-1009 and 1011 detect that the active state is changed to the inactive state within a stage and between stages for the mask bit of the mask information having the continuous active state and set the flags in active states. Then an OR gate 1002 and an AND gate 1010 which serve as the 2nd detecting means detect that the mask bit is changed again to the active state within the same bus cycle when the flags are kept under active states. Thus it is possible to avoid the transformation of the data and other faults owing to addition of such means that can detect a foul state of the mask information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to a bus control system that continuously transfers multiple bytes of data. In particular, it relates to means for updating the address and length of a data transfer with mask information representing the validity of the data.

〔overview〕

The present invention detects illegal activation of mask information in a bus control device in which mask information indicating the validity of the data is transferred together with data transferred in multiple stages, thereby preventing data errors based on invalid transfer data. It is designed to be able to prevent this.

[Conventional technology]

When data is transferred between a peripheral device and the main memory in a combiator system, the data to be transferred is the peripheral device → peripheral device control unit (hereinafter referred to as PCU) - input/output control unit (hereinafter referred to as IOD) → main memory. Storage device (hereinafter referred to as
It's called MMU. ), but a parallel bus configuration was used between the MMU and IOD or between the IOD and PCU, and multiple bytes were continuously transferred over several stages in one bus cycle to improve data transfer efficiency. For example, if data is transferred 4 times in a row on a 4-byte wide bus, 1 bus cycle will result in 1 data transfer.
Can transfer 6 bytes. In such a transfer method, M
Because all of the transferred data may not be valid due to the handling of word boundaries of memory addresses in the MU and the transfer length, add a mask bit to each byte to indicate whether or not it is valid data and transfer it together with the data. There are many.

[Problem that the invention seeks to solve]

Normally, the IOD manages memory addresses and data length during data transfer, but this update is
If mask information sent from the CU or mask information generated in the IOD is used, if a discontinuous mask appears in a bus cycle due to a hardware failure, the update will be incorrect and may cause data corruption. There was a drawback.

The present invention aims to eliminate this drawback and aims to provide a bus control device equipped with means capable of detecting fraudulent mask information.

[Means for solving problems]

The present invention provides a first detection means for detecting discontinuity in the active state of mask information based on a combination of the active state and inactive state of mask bits in one stage, and A flag means that detects that a mask bit transitions from an active state to an inactive state within a stage and between stages and activates a flag, and a flag means that activates a flag within the same bus cycle when the flag is active. It is characterized by comprising a second detection means for detecting that the state has returned to the normal state.

[Effect]

When discontinuity of mask information is detected based on the activation pattern of mask information within a stage, or after mask information changes to inactive between stages or within a stage of mask information where continuity is maintained, masking is performed again in the same bus cycle. If it detects activation, it will notify you of unauthorized data transfer.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of this embodiment.

In this embodiment, as shown in FIG. 1, a plurality of stages each having a plurality of data bytes are configured with data exchanged in one continuous bus cycle and mask bits corresponding to each data byte. , a data length 2 which is a means for transmitting and receiving mask information that becomes active when the data byte corresponding to this mask bit is valid, a mask register 3, an encoder 4, an address register 5, a length register 6, and an adder 7. , subtractor 8
and a memory access control circuit 9, a decoder 1001 which is a first detection means for detecting discontinuity in the active state of mask information based on a combination of active states and inactive states of mask bits in one stage, and an active state 1002.1003.1009.1011 (or game) which is a flag means that detects that mask bits of continuous mask information go from an active state to an inactive state within a stage and between stages, and sets a flag to an active state. , AND gate 1004.1006 and flip-flop 10
05.1007.1008 and the OR game which is the second detection means for detecting that the mask bit has returned to the active state within the same bus cycle when the flag is active)
1002 and an AND gate 1010.

The turnout processor 1 is connected to an IO bus to which an IO device control device (not shown) is connected, and controls the transmission and reception of data between a main memory (not shown) and the IO device control device. The input/output processor 1 includes a data register 2 for transmitting and receiving IO data, and a mask register 3 for transmitting and receiving 0 masks.
, an encoder 4 that encodes mask bits to generate address and length update values, an address register 5 that stores the address of the main memory, a length register 6 that stores the length of the transfer data, and the value of the address register 5. an adder 7 that updates the value of the length register 6, a subtracter 8 that updates the value of the length register 6, a memory access control circuit 9 that controls access to the main memory, and an illegal mask detection circuit 10 that checks the continuity of the mask. Become.

The IO path is composed of an IO data bus 20 and a 10 mask bus 21, and the IO data bus 20 has a transfer width of 4 bytes and can perform data transfer in 4 consecutive stages. That is, a maximum of 16 bytes can be transferred in one bus cycle. (2) The 0 mask bus 21 has a transfer width of 4 bits, and each bit corresponds to a byte position on the IO data bus 20. When a mask bit is logic "1", the corresponding byte is valid. Mask bits are generated on the IO device control device side when writing data to the memory, are generated by the memory access control circuit 9 when reading data from the memory, and are sent onto the process 0 mask bus 21.

The encoder 4 counts the number of logical "1" bits in the mask received from the IO mask bus 21 or the mask generated by the memory access control circuit 9, and sends the value encoded into 3 bits to the adder 7 and subtracter 8. Output. (The encoded value is a binary number from ro 00J to r
l Become OOJ. ) The memory access control circuit 9 generates an access address of the main memory based on the values of the address register 5 and length register 6 and performs memory access. When reading the memory, an IO mask is also generated based on the address and length. Further, upon receiving an error signal indicating detection of an incorrect mask from the incorrect mask detection circuit 10, the memory access is immediately stopped.

The illegal mask detection circuit 10 is a circuit that checks the continuity of masks in one bus cycle. FIG. 2 is a block diagram of the illegal mask detection circuit 10. This illegal mask detection circuit 10 detects mask discontinuity between one stage (i.e., ro 101J, rlool'', rlo
decoder 100 that outputs logic “1” (when the mask of “lo”, “1011” right and rl 101J is transferred)
1 and the OR game of mask 4 pits) 10
OR gate 100 that calculates the logical sum of 02 and the upper 3 bits
1004, a flip-flop 1005 that holds the state value of the least significant bit with a delay of one transfer cycle; 1
AND gate 1006, which calculates the logical sum of the output of 005 and the inverted value of the most significant bit of the mask.
Flip-flop 1007 is set when the output of 04 is logic "1", and flip-flop 10 is set when the output of 1006 is logic "1".
08, an OR game that calculates the logical sum of the output of the flip-flop 1007 and the output of the flip-flop 1008) 1
009, the output of OR gate 1002, and OR gate 10
and an AND gate 1010 that performs a logical product with the output of 09;
OR gate 10 which takes the logical sum of the output of decoder 1001 and the output of 1010 and provides the output as a mask fraud signal to memory access control circuit 9.
It consists of 11 parts. The output of flip-flop 1007 is a flag indicating that valid data has ended within one stage, and the output of flip-flop 1008 is a flag indicating that valid data has ended between stages.

FIGS. 3 to 5 are time charts of the embodiment of the present invention, and the operation of the fraudulent mask detection circuit 10 will be explained using FIGS. 2 to 5. As shown in FIG. 3, the 10-device control device is transmitting data and masks in 4 consecutive stages at stage 1°, and the mask transmitted at stage t is I.
Assume that discontinuity occurs due to a failure in the mask generation circuit of the O device control device. The value output from the encoder 4 at stage t is "3", and the update of the address and length is shifted by 1 from the original value, but the decoder 1002
Since this is detected and notified to the memory access control circuit 9, writing to the main memory is stopped.

Further, as shown in FIG. 4, after the -degree mask becomes "0" at stage t2, the mask becomes "0" again at stage t4.
1”, the following operation is performed. The mask value taken into register 3 at stage t is rl 1
10J, indicating that the flip-flop 1007 is set and valid data is interrupted. stage t,
When the mask becomes valid again, the output value of the OR gate 1002 becomes "1", the output value of the Ant Gate 1010 becomes "1", and the memory access control circuit 9 is notified of the error.

Also, as shown in FIG. 5, stage 1. In this case, the mask is "1" for all 4 bits, but at stage t2, the mask becomes all "0", and at stage t.

In cases where the mask is generated again after Flip-flop 1 at stage t3
005 holds the value "1" of the least significant bit stored in the mask register 3 of stage t2. Similarly, since the most significant bit of the mask stored in the mask register 3 at stage t3 is "0", the output of the AND gate 1006 becomes "1", and at stage t4, the output of the flip-flop 1006 becomes "1".
08 is set. At this time, since the mask written to the mask register 3 at stage t4 is ro 001J, the output value of the OR game) 1002 becomes "1", an error is notified to the memory access control circuit 9, and the memory write operation is stopped. Canceled.

In this embodiment, the write direction to the main memory has been explained, but the memory read direction can be checked in the same way. In this case, the mask generated by the memory access control circuit 9 and sent onto the bus is checked.

〔Effect of the invention〕

As explained above, the present invention is able to check the authenticity of mask information on the bus, thereby preventing problems such as garbled data due to mask fraud and improving the reliability of the bus system. There is.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of an unauthorized mask detection circuit that is a component of the embodiment of the present invention. 3 to 5 are time charts showing the operation of the embodiment of the present invention. 1...I/O processor, 2...Data register,
3...Mask register, 4...Encoder, 5...
・Address register, 6...Length register, 7・
...Adder, 8...Subtractor, 9...Memory access control circuit, 10...Illegal mask detection circuit, 20...
IO data bus, 21...IO mask bus, 1001
...Decoder, 1002.10031009.101
1...Orgate, 1004.1006.1010・
...And Gate, 1005.1007.1008...
·flip flop. WJ 2 mouths

Claims (1)

[Claims] (1) A plurality of stages each having a plurality of data bytes are configured with data that is exchanged in one continuous bus cycle, as well as a mask bit corresponding to each data byte, and the data byte corresponding to this mask bit is In a bus control device equipped with a means for exchanging mask information that becomes active when it is valid, the active state of the mask information is determined based on a combination of the active state and inactive state of mask bits in one stage. a first detection means for detecting continuity, and a flag for detecting that mask bits of mask information whose active states are continuous transition from an active state to an inactive state within a stage and between stages, and setting the flag to an active state. and second detection means for detecting that the mask bit has returned to the active state within the same bus cycle when the flag is in the active state.