JPH01145754A - Data transfer system - Google Patents

Abstract

PURPOSE:To extend a data bus without increasing the number of bus lines by informing only a head address to a slave, and thereafter, diverting a system address bus to a system data bus and executing a data transfer. CONSTITUTION:A module having a DMA function is provided with plural data buffers 24, 25 being equal to width of a system data bus, and in case of executing a continuous address access to a slave by using a system bus 27, only a head address is informed to the slave, and thereafter, a system address bus is diverted to the system data bus, and through those data buffers 24, 25, the data transfer is executed by both the system data bus and the system address bus. In such a way, a transfer speed on the system bus can be improved by extending the width of the data bus without increasing the number of data lines.

Description

TECHNICAL FIELD The present invention relates to a data transfer method for a computer system, and more particularly to a data transfer method that allows expansion of a data bus without increasing the number of path lines.

BACKGROUND TECHNOLOGY In general, in a computer system, when transferring a large amount of data between memories, it is transferred directly to the memory access controller (hereinafter referred to as DMAC) without going through the central processing unit (hereinafter referred to as CPU). Data transfer is performed using the system bus.

For example, as shown in FIG. 6, a memory 61,
In a computer system in which modules such as a DMAC 62 and a CPU 63 are connected by a system bus, address-data bus separation methods and address-data bus multiplexing methods are known as data transfer methods using the system bus.

This address-data bus separation method is shown in Figure 4.
The address signal (Strobe) is applied to the address bus and data bus path lines by a strobe signal (Strobe).
AD) and data signals (Data) are transferred simultaneously. Therefore, the data transfer speed is high.

However, this method requires a large number of pass lines, which is problematic in view of the recent trend toward expansion of address buses and data buses.

Further, in the address-data bus multiplexing method, addresses and data are transferred alternately on the same path line, as shown in FIG. Therefore, the number of pass lines can be reduced.

However, since this method cannot output addresses and data at the same time, there is a problem that the data transfer speed is lower than that of an address-data bus separation type bus having the same data bus width.

Furthermore, as a method for transferring data to consecutive addresses, it has been proposed to notify only the Sawara address to the slave when accessing consecutive addresses, and then count up the address on the slave side, as shown in Figure 3. .

However, this method does not take into consideration the effective use of the pass line.

Purpose The purpose of the present invention is to improve the above-mentioned problems and to provide a data transfer method that can expand the data bus width and improve the transfer speed on the system bus without increasing the number of data lines. It is about providing. - Configuration In order to achieve the above object, the data transfer method of the present invention has the following features:
In the data transfer method of a computer system in which a module having a DMA function is connected with modules such as a CPU and memory by a system bus, the above D.
A module with an MA function is equipped with multiple data buffers equal to the system data bus width, and when performing continuous address access to a slave using the system bus, only the first address is notified to the slave, and then the system address bus is connected to the system data bus. The feature is that data is transferred to a bus, and data is transferred via both a system data bus and a system address bus via these data buffers.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a timing chart showing data transfer to consecutive addresses in an embodiment of the present invention.

FIG. 2 is a configuration diagram of a board having a DMA function in a computer system according to an embodiment of the present invention.

The board having the DMA function in the computer system of this embodiment has a memory (MEMORY) function as shown in FIG.
)21, DMAC22, CPU23, data buffer A
24, a data buffer B 25, an address latch 26, and a local bus (local data bus, local address bus), and is coupled by a system bus 27 with other modules such as memory (not shown).

Furthermore, the local bus is 32 bits, and the system data bus is 16 bits (32 bits during DMA).

In addition, as shown in FIG. 1, when data is transferred to consecutive addresses (in DMA), the DMAC 22 first uses the address strobe signal (AS) to transfer the first address to the slave (in the figure) using the system address bus of the system bus 27. (not shown) and then expands the system data bus by repurposing the system address bus to perform high-speed data transfer using both path lines.

In other words, when performing DMA, the DMAC 22 uses the data buffer A 24 and the data buffer B 25, thereby reducing the
2-bit data transfer can be performed.

Note that the address is generated by the slave CPU board (not shown) itself counting up the first address.

Furthermore, when the CPU 23 accesses the system bus 29, it performs 16-bit data transfer using the address latch 26 and data buffer A24.

In this embodiment, it is possible to expand the data bus without increasing the number of path lines and without creating a large overhead unlike the general address-data bus multiplexing system. For this reason, especially image processing devices, etc.
To improve the processing speed of a system that often transfers a large amount of data by DMA.

Effects According to the present invention, it is possible to expand the data bus without increasing the number of path lines, and therefore it is possible to realize faster data transfer.

Furthermore, since it can be configured using existing path lines, it can be easily added to existing systems.

Furthermore, since the number of pass lines is small compared to the data bus width, economical efficiency is improved.

[Brief explanation of the drawing]

FIG. 1 is a timing chart showing data transfer to consecutive addresses in one embodiment of the present invention, FIG. 2 is a configuration diagram of a computer system in one embodiment of the present invention, and FIG.
The figure is a timing chart explaining data transfer to consecutive addresses using the conventional method, FIG. 4 is a timing chart explaining the conventional address-data bus separation method, and FIG.
The figure is a timing chart explaining a conventional address-data bus multiplexing system, and FIG. 6 is a configuration diagram of a conventional computer system. 21.61: MEMORY, 22,62:
Direct Memory Access Controller (DMA)
C), 23, 63: Central processing unit (CPU). 24: Data buffer A, 25: Data buffer B, 2
6: Address latch, 27: System bus. AD near address signal, AS near address strobe signal, Data: data signal, DS: data strobe signal, S trobe near strobe signal. CN ('J
L~Figure 3 Figure 5trCkB Figure 5 Figure 6

Claims (1)

[Claims] 1. In the data transfer method of a computer system in which a module having a DMA function is connected with modules such as a CPU and memory by a system bus, the above D
A module with an MA function is equipped with multiple data buffers equal to the width of the system data bus, and when performing continuous address access to a slave using the system bus, only the first address is notified to the slave via the system address bus, and then A data transfer method characterized by expanding the system data bus by converting a system address bus into a system data bus, and performing data transfer using a plurality of the data buffers.