JPH01146196A - Refreshing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a DRAM refresh method,
From the outside, it appears as if the refresh operation is unnecessary.
It is intended to provide RAM.

[Conventional technology]

A conventional example is a CPU as described in Japanese Patent Application Laid-Open No. 61-45493.
Similarly, attempts are being made to control refresh from outside the memory, and current peak value control is also attempted to be distributed outside the memory IC for each IC, as described in Japanese Patent Laid-Open No. 60-13397.

[Problem that the invention seeks to solve]

Since the above-mentioned conventional technology performs refresh control outside the IC memory, there are inconveniences such as the control circuit cannot be accessed from the CPU during refresh.

The object of the present invention is to provide a RAM that can be accessed at all times and a memory that has a small refresh peak current value.

[Means for solving problems]

The above purpose is to provide a refresh Y decoder that is independent of a Y decoder that stores data in a row in a memory cell matrix at a row address specified externally, and to
A path arbiter that determines whether a specific row of data is connected to the decoder allows external access and internal refresh to be compatible, and at the same time allows refresh to be performed at a cycle determined by the number of rows to be refreshed and memory cell discharge characteristics, and at the same time divides rewriting. By doing so, the refresh current and its peak current can be reduced.

[Effect]

When there is an external access, the X row access determination unit transfers the external access row (Xi row) to the memory cell matrix (m rows and n columns).
n pieces of data in the Xi rows of the memory cell matrix are sent to the Y decoder A (for reading and writing, as in the conventional case), and are stored therein.

Thereafter, if there is a row (Xi row) to be refreshed, n pieces of data from X5 rows of the memory cell matrix are sent to Y decoder B (newly installed for refresh) and sent back to perform waveform shaping, that is, refresh.

When the input/output processing of Y decoder A is completed, the connection between the memory cell matrix and Y decoder B is changed to Y decoder A, and the data of decoder A is transferred to Xi of the memory cell matrix.
By writing to a row, both normal access and refresh can be achieved.

〔Example〕

The present invention will be explained below with reference to FIGS. 1 to 3.

FIG. 1 shows one embodiment of the present invention, FIG. 2 shows the timing of main signal lines during memory operation, and FIG. 3 shows the timing in standby state.

First, the configuration of the present invention will be described with reference to FIG.

■ The memory section that stores information is arranged in a matrix (m rows and n
When the position of the X row is determined by the signal line 104 that specifies the row, n pieces of data of that row are sent to the signal line 106 via the signal switching circuit 2. Memory cell matrix 1゜ outputs the information to Y decoder A6 or Y decoder B7, and also receives the information from there ■ External X via address buffer 9 for address system signals
An address signal line 101, an address signal line 112 for the row to be refreshed from the refresh control unit 4, a signal line 108 for sending a write end signal from the Y decoder B, etc. are connected, and these signals are used to read the rows of the memory matrix. Outputting a specified signal to the signal line 104 and outputting a signal for connecting the signal lines 106 and 105 to the external access signal switching circuit 2 to the signal line 103, and writing from Y decoders A and B to the memory cell matrix 1. X row access determining unit 5° which sends those row data to the refresh control unit 4 via the signal line 113 upon completion of the process. ■ A signal switching circuit that operates to connect the signal lines 106 and 105 using the signal on the signal line 103 only at the time of external address. 2 (103
signal line 106 is connected to 107).

■ When driving an external address, the data in a certain row of the memory matrix 1 is received through the signal lines 105, 106 and the signal switching circuit 2, and the Y-based address signal is received from the signal line 102 via the address buffer 9, and the specified A function to switch between two modes: an output mode in which the address signal is output from the D out buffer 10 via the signal line 110, and an input mode in which the input signal is received via the Din buffer 8 and its signal line 109, and their operations (input or
After output), in order to reproduce data in memory cell matrix 1, signal lines 105 and 106 operate to send data from decoder A back to memory cell matrix 1 in the opposite direction to signal switching circuit 2. Memory cell matrix The n pieces of data in one row to be refreshed are read through the signal lines 106, 107 and the signal switching circuit 2, and written in the same row, and the X row access determination unit 5 indicates the end of writing via the signal line 108.
Y decoder B7゜■
Receives the X address of the row that has been written into the memory cell matrix 1 from decoder A or B, records the address at the end of the permutation of rows to be refreshed, and sends a signal from the refresh control signal generator that determines the refresh time. A signal sent through a line 111 sends the first X address of the permutation to the X row access determination unit 5 through a signal line 112, and the total number of rows requiring refresh is sent to the refresh control signal generation unit 10 through a signal line 114 as data for determining the refresh cycle. The refresh control unit 4゜■ operates to send information to the memory cell matrix.
A refresh control signal that operates to determine a refresh time based on signals from a signal line 115 that transmits on the F line and a signal line 114 that transmits the number of rows to be refreshed, and sends it to the refresh control unit 4 via a signal line 111. Generation Unit 3 Next, the operation will be explained using an example in which row i and column i of memory matrix 1 are accessed from the outside and row j is refreshed.

First, the X address Xi row signal is outputted to the signal line 101 via the address buffer 9 as shown in FIG. Then, the X row access determination unit outputs signals as shown to the signal lines 103 and 104 to
The i-row data is sent to the Y decoder 6 via the signal lines 106 and 105 and the signal switching circuit 2.

At the same time, the Xi address is sent to the signal line 113 to remove the Xi address from the permutation of the refresh queue in the refresh control unit 4, and the row after the Xi address is shifted to fill the hole where Xi is missing.

When the time to refresh (denoted as Ti in FIG. 2) comes, the refresh control signal generator 3 outputs a signal to the signal line 111.
A signal is output to Xj, and the first row Xj address of the refresh queue of the refresh control section 4 is sent to the X row access determination section 5 via the signal line 112. The determining unit 5 separately stores the Xi address and sends the Xj address to the signal line 104. Since the signal switching circuit 2 connects the signals tii 106 and 109, it can send the data of Xi of the memory cell matrix 1 to the Y decoder B7. Memory cell matrix 1 using the same data and the same route
Refreshing is performed by writing to the Xi row of .

When writing is completed and completion information is output to the signal line 108, the determining unit 5 causes the X5 row address to be set at the end of the queue in the control unit 4.

Let's go back in time a little earlier than Tj and explain the data processing of Y decoder A6.At time 0 Ti, when Y-system address Yi column data is output to the signal line 102, the i-th column data of 6 is signaled to the Y decoder. ! ! Output via 110 (Re
(ad mode) or input the input data via the Din buffer 8 and signal line 109 to the i column (Write mode),
Then, the access determining unit 5 detects the change in the signal line 101, outputs a signal to the signal line 103 to cause the signal switching circuit 2 to connect the signal lines 105 and 106, and outputs the stored Xi address to the signal line 104. Then, the information of Y decoder A6 is written to row Xi of memory cell matrix 1. At the same time, the signal Xi is output to the signal line 113, and the refresh control unit 4 sets the Xi address to the end of the refresh queue. If the time to refresh is Tj
In order to prioritize external access, the cycle of the signal generator is set so that the refresh operation is suspended for a certain period of time.

The standby state will be explained with reference to FIG.

Since it is not driven by an external address, the signal line 113 is in the "H" state. Therefore, the signal switching circuit connects signal lines 106 and 109. When the nine rows to be refreshed are input to the determining unit 5, the rows are output to the signal line 104, so the memory cell matrix 1 connects the rows to the signal line 106.
Output to.

The subsequent operations are similar to those described above.

In this way, refresh can be performed both during operation and in standby mode.

〔Effect of the invention〕

According to the present invention, since the memory user side does not need to consider refresh, the circuit required for this becomes unnecessary, and the refresh time of about 200m5 every 4+m5 (in the case of 256K DRAM) is also unnecessary. Utilization efficiency increases.

For manufacturers, this has the effect of shortening refresh-related testing time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. Figure 3 is a diagram showing the timing of the main signals 61...
・Memory cell matrix, 2...signal switching circuit, 3
... Refresh control signal generation unit, 4... Refresh control unit, 5... X row access determination unit, 6... Y
Decoder A (normal reading and writing), 7...Y decoder B
(for refresh), 8...Din buffer, 9...
・Address buffer, 10...D out buffer,
101...Signal line (for external X row address), 102...
... Signal 1 (for external Y column address), 103 ... Signal line (for connecting signal lines 105 and 106 of the signal switching circuit), 1
04... Signal line (for row setting of memory cell matrix), 105... Signal line (for memory cell column information), 1
06-107...Same as above, 10B...Signal line (Y decoder B write end signal), 109...Signal line,
(input signal), 110... signal line (output signal), 11
1...Signal line (refresh start signal), 112...
・Signal line (line to be refreshed), 113...Signal line (line for registering or deleting refresh queue), 114
...Signal line (total number of rows to be refreshed), 20th Ishi 1jYJ7)

Claims (1)

[Claims] 1. When the memory is accessed from an external CPU, etc., all data in the accessed row (assuming that the information recording section forms a matrix of m rows and n columns) is stored in Y A new independent Y decoder is provided inside the memory, which outputs to a block called a decoder, and if there is a row to be refreshed during column address signal processing and input/output processing time of the former Y decoder, the data of that row is called to the latter decoder. A refresh circuit characterized in that it is configured to write data. 2. In claim 1, if the number of columns of the memory cell matrix is n, the Y decoder section holds n pieces of data, and rewrites the n pieces of data by dividing it into two or more times. A refresh circuit characterized in that it is configured to reduce the peak value of a refresh current by increasing the refresh current. 3. In claim 1, when registering the rows to be refreshed, only the rows accessed from the outside are registered,
A refresh circuit characterized in that the refresh circuit is configured to reduce refresh current when the number of registered rows is small. 4. Refreshing according to claim 1 or 3, characterized in that the time interval between the rows to be refreshed depends on the discharge characteristics in the memory cells and the number of registered rows to be refreshed. circuit.