JPH01149111A - Communication method between programmable controller and host cpu - Google Patents

Communication method between programmable controller and host cpu

Info

Publication number
JPH01149111A
JPH01149111A JP30747387A JP30747387A JPH01149111A JP H01149111 A JPH01149111 A JP H01149111A JP 30747387 A JP30747387 A JP 30747387A JP 30747387 A JP30747387 A JP 30747387A JP H01149111 A JPH01149111 A JP H01149111A
Authority
JP
Japan
Prior art keywords
response
host cpu
command
communication method
programmable controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30747387A
Other languages
Japanese (ja)
Inventor
Kenichi Kawakami
川上 健一
Toru Shigeoka
重岡 徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Manufacturing Co Ltd filed Critical Yaskawa Electric Manufacturing Co Ltd
Priority to JP30747387A priority Critical patent/JPH01149111A/en
Publication of JPH01149111A publication Critical patent/JPH01149111A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は上位CPUと複数のプログラマブルコントロー
ラ(以下PCと称す)間でデータの相互授受を行う場合
の通信方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication method for mutually exchanging data between a host CPU and a plurality of programmable controllers (hereinafter referred to as PCs).

〔従来の技術〕[Conventional technology]

従来、PCと上位CPUとの間の通信手順はコマンド、
レスポンスの関係が半2重の通信方式が使用されていた
Conventionally, the communication procedure between a PC and a host CPU is based on commands,
A communication method with half-duplex response was used.

PCと上位CPUの動作は次の通りである(第3図参照
)、上位CPUは通信可能状態になるとコマンFCMD
を作成し、PCにコマンドCMDを送る。上位CPUは
PCに対してのコマンド送信を完了するとPCからのレ
スポンスR3Pを待つ状態となる。PCは上位CPUか
らコマンドCMDを受け取ると、そのコマンドCMDを
処理し、レスポンスR3Pを作成し、上位CPUへ送信
する。PCは上位CPUに対してのレスポンス送信を完
了すると、コマンド待ち状態となる。上位CPUはPC
からのレスポンスRSPを受け取り、それを処理(表示
等)すると通信可能状態となる。
The operation of the PC and the host CPU is as follows (see Figure 3).When the host CPU becomes ready for communication, it issues the command FCMD.
Create and send command CMD to the PC. When the host CPU completes sending the command to the PC, it enters a state in which it waits for a response R3P from the PC. When the PC receives the command CMD from the higher CPU, it processes the command CMD, creates a response R3P, and sends it to the higher CPU. When the PC completes sending the response to the upper CPU, it enters a command waiting state. Upper CPU is PC
When the response RSP is received from the server and processed (displayed, etc.), it becomes communicable.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の通信方法では、上位CPUはPCに、コ
マンドを送った後PCからのレスポンスが返って来るま
で待ち状態となり、このとき対象データの瞼が多い場合
、あるいはデータの処理が短時間に完了しない場合には
PCのレスポンス送信までに長時間を要し、レスポンス
が上位CPIIに返るまでに長時間を要し、上位CPU
の通信処理での待ち時間が大きくなり通信処理の効率が
低下するという欠点がある。特に複数のPCがスレーブ
として上位CPUに接続される場合、この不具合が顕著
となる。
In the conventional communication method described above, the host CPU sends a command to the PC and then waits until a response is returned from the PC. If it is not completed, it takes a long time for the PC to send a response, it takes a long time for the response to return to the upper CPII, and the upper CPU
The disadvantage is that the waiting time in communication processing increases and the efficiency of communication processing decreases. This problem becomes particularly noticeable when a plurality of PCs are connected to a host CPU as slaves.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のプログラマブルコントローラと上位CPU間の
通信方法は、PCは上位CPUからコマンドを受け取る
と、そのコマンドを処理する前に受信確認レスポンスを
上位CPUに返し、その後上位CPUからポーリングコ
マンドが送信されると、PCはコマンド処理が終ってい
れば本来のレスポンスを上位CPUに返す。
In the communication method between the programmable controller and the host CPU of the present invention, when the PC receives a command from the host CPU, the PC returns a reception confirmation response to the host CPU before processing the command, and then a polling command is sent from the host CPU. If the command processing is completed, the PC returns the original response to the upper CPU.

〔作用〕[Effect]

したがって、上位CPUはPCがコマンド処理を行なっ
ている間レスポンス待ち状態にならずに他のPCとの通
信を行なえ、複数のPCスレーブとの通信の効率を高め
ることができる。
Therefore, while the PC is processing a command, the host CPU can communicate with other PCs without waiting for a response, and can improve the efficiency of communication with a plurality of PC slaves.

〔実施例〕〔Example〕

次に1本発明の実施例について図面を参照して説明する
Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明のプログラマブルコントローラと上位C
PU間の通信方法の一実施例のシーケンス図、第2図は
上位CPUとPCとからなるシステム構成図である。
Figure 1 shows the programmable controller of the present invention and the upper C
FIG. 2 is a sequence diagram of an embodiment of a communication method between PUs, and is a system configuration diagram consisting of a host CPU and a PC.

上位CPUIはコマンドCMDを作成し、PC2に送る
。上位CPUIはPC2に対してのコマンド送信を完了
すると、PCZからのレスポンスR3Pを待つ状態とな
る。PC2は上位cptriからコマンドCMDを受信
部3で受け取ると、コマンド解析部4で該コマンドCM
Dを解析し、レスポンス作成部6でA CK ”レスポ
ンスを作成し、コマンドCMDを処理部5で処理する前
に上位CPUIに対して“ACK”レスポンス作成部7
より返す、上位CPUIは“A CK ”レスポンス−
を受け取ると、通信可能状態となる。PC2はACK”
レスポンスを返した後、受け取ったコマンドCMDの処
理を処理部5で始める。上位CPUIは、本来のコマン
FCMDに対するレスポンスRSPを要求するため“P
OLL” =+ffンドを作成し、PC2へ送信する。
The upper CPUI creates a command CMD and sends it to the PC2. When the host CPUI completes sending the command to the PC2, it enters a state where it waits for a response R3P from the PCZ. When the receiving unit 3 receives the command CMD from the upper cptri, the PC 2 analyzes the command CM in the command analyzing unit 4.
D is analyzed, the response creation unit 6 creates an "ACK" response, and before the command CMD is processed by the processing unit 5, the response creation unit 7 sends an "ACK" response to the upper CPUI.
The upper CPUI returns an “ACK” response.
When received, communication becomes possible. PC2 is ACK”
After returning the response, the processing unit 5 starts processing the received command CMD. The upper CPUI requests “P” to request a response RSP to the original command FCMD.
OLL" = +ff is created and sent to PC2.

PC2は“POLL”コマンドを受信部3で受け取ると
、レスポンス作成部6でそのレスポンスに本来のレスポ
ンスRSPを付加して送信部7より上位CPUIへ返信
する。上位cpuiはそのレスポンスR3Pを受け取る
とレスポンスR3Pに対する処理(表示等)を行ない、
通信可能状態に戻る。
When the receiving section 3 of the PC 2 receives the "POLL" command, the response generating section 6 adds the original response RSP to the response and sends it back to the higher-level CPUI from the transmitting section 7. Upon receiving the response R3P, the upper CPU performs processing (display, etc.) on the response R3P,
Return to communicable state.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、PCが本来のレスポンス
を送信する前に確認レスポンスを上位CPUに返信し、
その後上位CPUからポーリングコマンドが送信された
とき、本来のレスポンスを送信することにより、上位C
PUは、PCがコマンドを処理している間、通信可能状
態になるので、他のPCスレーブとの通信を行なえ、複
数のPCスレーブとの通信の効率を高めることができる
効果がある。
As explained above, the present invention allows the PC to send a confirmation response back to the upper CPU before sending the original response,
After that, when a polling command is sent from the upper CPU, by sending the original response, the upper CPU
Since the PU is in a communicable state while the PC is processing commands, it can communicate with other PC slaves, which has the effect of increasing the efficiency of communication with multiple PC slaves.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のPCと上位CPU間の通信方法の一実
施例を示すシーケンス、第2図はPCと上位CPUのシ
ステム構成図、第3図は従来の方法を示すシーケンス図
である。 1・・・上位CPU、   2・・・PCl3・・・受
信部、    4・・・コマンド解析部、5・・・処理
部、    6・・・レスポンス作成部、7・・・送信
部。 特許出願人  株式会社安川電機製作所代 理 人  
弁理士 若林  忠 朗セCPUI              PC2第1
FIG. 1 is a sequence diagram showing an embodiment of the communication method between a PC and a host CPU of the present invention, FIG. 2 is a system configuration diagram of a PC and a host CPU, and FIG. 3 is a sequence diagram showing a conventional method. DESCRIPTION OF SYMBOLS 1... Upper CPU, 2... PCl3... Receiving section, 4... Command analysis section, 5... Processing section, 6... Response creation section, 7... Transmission section. Patent applicant Yaskawa Electric Co., Ltd. Agent
Patent Attorney Tadaaki Wakabayashi CPUI PC2 No. 1
Cause

Claims (1)

【特許請求の範囲】[Claims] プログラマブルコントローラは上位CPUからコマンド
を受け取ると、そのコマンドを処理する前に受信確認レ
スポンスを上位CPUに返し、その後上位CPUからポ
ーリングコマンドが送信されると、プログラマブルコン
トローラはコマンド処理が終っていれば本来のレスポン
スを上位CPUに返す、プログラマブルコントローラと
上位CPU間の通信方法。
When the programmable controller receives a command from the host CPU, it returns a reception confirmation response to the host CPU before processing the command, and then when the host CPU sends a polling command, the programmable controller returns the A communication method between a programmable controller and a host CPU that returns a response to the host CPU.
JP30747387A 1987-12-07 1987-12-07 Communication method between programmable controller and host cpu Pending JPH01149111A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30747387A JPH01149111A (en) 1987-12-07 1987-12-07 Communication method between programmable controller and host cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30747387A JPH01149111A (en) 1987-12-07 1987-12-07 Communication method between programmable controller and host cpu

Publications (1)

Publication Number Publication Date
JPH01149111A true JPH01149111A (en) 1989-06-12

Family

ID=17969501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30747387A Pending JPH01149111A (en) 1987-12-07 1987-12-07 Communication method between programmable controller and host cpu

Country Status (1)

Country Link
JP (1) JPH01149111A (en)

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