JPH01149267A - Demodulating circuit for digital reproducing device - Google Patents

Abstract

PURPOSE:To prevent an error from being propagated by counting the number of data in one word of serial reproducing data and inverting the data when a counted value goes to a prescribed value. CONSTITUTION:Concerning the serial reproducing data from a demodulating circuit, data '1' in one word are counted by a '1' counter according to a reset signal 21 from a frame synchronization detecting circuit 8. Here, since an 8/10NRZ is used in a record modulating system, when the data of '0' or '1' in one word are obtained as a maximum '6' and a counted value proceeds up to a '7', an inverting signal 22 is outputted from a data inverting circuit 9 and for the erroneous serial reproducing data, the data '1' are inverted to the '1' by an exclusive gate 11. Thus, the drop-out of one bit of an (n)-word is prevented from being propagated to a next (n+1) word.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a demodulation circuit for a digital playback device that plays back digital signals recorded on a recording medium.

(Prior art) In digital recording and reproducing devices, a block code structure is used in which data words are divided and error correction words are added to detect and correct errors during reproduction, and burst errors caused by scratches on the recording medium are dispersed as random errors. The data is interleaved and recorded on a recording medium in order to improve the error correction ability.

FIG. 4 is a block diagram showing an example of a conventional decoded signal processing circuit for decoding data having the data structure shown in FIG.

The analog signal reproduced from the recording medium is sent to the demodulation circuit (1 to
6), the digital playback data is demodulated and the PL
A reproduced clock is generated by the L circuit 7. Based on these two signals, the frame synchronization detection circuit 8 extracts a synchronization pattern, separates data words, and the decoding circuit 9 detects and corrects errors. be.

With high-density recording, the probability of random errors occurring increases, and the pit error rate is as high as 10-3 to 10-4, most of which are 1-bit errors. In the conventional method of demodulating reproduced data using a demodulation circuit, this 1-bit dropout causes uncertainty as described below.

FIG. 6 is a diagram showing the timing until demodulating arbitrary two words of parallel reproduction data when 8/10NRZ modulation is used as an example of the recording modulation method.

Figure 7 is a diagram showing the timing when a dropout occurs at the location marked ■ in Figure 6.
This shows that a bit dropout propagates into a 2-word error up to n+1 words. Also PLL
15 bits are lost in the phase comparison input, and the reproduced clock becomes unstable.Depending on the jitter of the reproduced data of n+2 words, a 1-bit dropout may extend to 3 words.In the conventional demodulation circuit, when a dropout occurs, the reproduction clock becomes unstable. The reproduced data demodulation operation was uncertain.

Furthermore, when a dropout occurs in the minimum magnetization reflection pattern (■) in Figure 6, the conventional method is to simply demodulate the erroneous digital reproduction data in the demodulation circuit, and the decoding circuit performs error detection and error correction. However, by adding a simple circuit, it is possible to detect/correct 1-bit dropouts in the demodulation circuit, thereby increasing the error correction ability of the decoding circuit.

(Problems to be Solved by the Invention) As described above, the conventional digital reproduction data demodulation method using a demodulation circuit has the drawback that when dropout occurs, errors propagate depending on the location where the dropout occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a demodulation circuit in which errors are not propagated and a demodulation circuit for a digital reproducing device that performs error correction using a minimum magnetization reversal pattern.

[Structure of the invention]

(Means for solving the problem) When 8/10NRZ modulation is used as the recording modulation method, the maximum number of data '0' or 1' in one word is fixed, so the data in one word A counting circuit that counts '0' or data '1' prevents the propagation of errors by inverting the digitally reproduced data when the maximum value is reached, and at the minimum magnetization reversal interval, the positive phase output and the opposite phase of the level detection circuit are used. By counting the interval using the output, a 1-bit dropout detection and error correction circuit is inserted into the demodulation circuit, which prevents data errors from extending over several words, and enables the minimum magnetization reversal interval. Since error correction is performed in the demodulation circuit, the error correction capability of the decoding circuit can be improved.

(Embodiment) FIG. 1 is a block diagram of a demodulation circuit portion showing an embodiment of the present invention. In the conventional example shown in FIG. The configuration is such that data inversion gates 11, 12 and 13 are added.

FIGS. 2 and 3 are timing charts showing a schematic operation according to the present invention.

1 to 3 regarding the operation of the circuit added according to the present invention.
This will be explained using figures. However, both FIGS. 2 and 3 show dropout on the negative phase side, and the dropout operation on the positive phase side is omitted because it is the same as that on the negative phase side.

In FIG. 2, the data inversion circuit 9 converts the serial reproduction data 20 from the demodulation circuit into a '1' counter that counts data '1' in one word by a reset signal @21 from the frame synchronization detection circuit 8. Initially, since 8/1ONRZ is used as the recording modulation method, one word of O'
Or, if the maximum number of '1' data is '6', when the counter value advances to '7', the inverted signal 22 is output and the erroneous serial reproduction data 20 is transferred to the exclusive gate 1.
By inverting the data '1' to 0 at 1, 1-bit dropout of n word is prevented from propagating to the next n+1 word, and it can also be supplied to the phase comparison input to PLL, stabilizing PLL operation. It can be done.

In FIG. 3, the minimum magnetization reversal 1-bit dropout detection/correction circuit 10 performs error detection/correction by using the positive phase pulse 30 and negative phase pulse 31 from the level detection circuit 5. The latch D is a latch that is set by a positive phase pulse 30 and reset by a negative phase pulse 31. When a negative phase dropout occurs, the next positive phase pulse 30 is input while the latch D is not reset and remains set, so the latch E is set at this point.

When latch E is set, latch F, which synchronizes with the reproduced clock of the next stage, is set by one clock width and the inverted signal 32 is set.
is output and the data '1' is inverted to '0' by the erroneous serial reproduction data 33 and exclusive gate 13, and 1-bit dropout error correction at the time of minimum magnetization reversal is performed.

By adding circuits for both cases in this manner, digital reproduction data can be reliably obtained in the demodulation circuit.

(Effects of the Invention) According to the present invention, when a dropout occurs, the error is corrected in the demodulation circuit without propagating the error, and if the dropout is a 1-bit dropout at the minimum magnetization reversal, the decoding circuit The error correction ability of the system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a demodulation circuit showing an embodiment of the present invention;
Fig. 2 is a timing chart showing that the generated dropout does not propagate to the next word, Fig. 3 is a timing chart showing 1-bit dropout error correction operation with the minimum magnetization reversal interval, and Fig. 4 is a timing chart of the conventional example. A block diagram of the decoded signal processing circuit, Fig. 5 is a data configuration diagram, Fig. 6 is a timing chart of the demodulation circuit when dropout does not occur in the conventional example, and Fig. 7 shows the following when dropout occurs in the conventional example. 3 is a timing chart showing that an error is propagated to a word of . 9... Data inversion circuit 10... 1-bit dropout detection/correction circuit Representative Patent attorney Nori Chika 1 is the same Mitsuyuki Matsuyama Figure 2 Figure 3 Figure 6 Figure 7

Claims (2)

[Claims] (1) The demodulation circuit of a digital playback device that obtains digital playback data from an analog signal played back from a recording medium is equipped with a counting circuit that counts the number of data '0' or '1' in one word of serial playback data. , when the count value of data '0' or '1' reaches a predetermined number, data '0' is changed to '
1', data '1' is inverted to '0' to prevent error propagation. (2) It is characterized by comprising a dropout detection circuit when the data interval is the minimum magnetization interval, and an error correction circuit that performs 1-bit error correction when the detection circuit detects a 1-bit dropout. A demodulation circuit for a digital playback device according to claim 1.