JPH01149471A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a source and drain from an excessive lateral expansion by a method wherein the gate electrode on a gate insulating film of a specified thickness serves as a mask, a specified dose of phosphorus is ion-implanted, etching is accomplished on both edges of the gate electrode along its length before the formation of an insulating film of a specified length on the side walls, and a high concentration of arsenic ions is implanted. CONSTITUTION:On a P-type semiconductor silicon substrate 1, there exist a 150-300Angstrom -thick gate oxide film 12 for example built of silicon oxide, a gate electrode 13, and a source 14 and a drain 15 both implanted with a 1X10<14>cm<-2> or lower concentration of phosphorus ions. Thereon, an insulating film 16, for example a silicon oxide film, is deposited. A reactive ion etching process is accomplished to affect the insulating film 16, which results in side-wall insulating films 17 and 17, on both edges of the gate electrode 13 along its length. The side wall insulating films 17 and 17' should be not less than 0.2mum in width W. A source electrode 18 and a drain electrode 19, both high in impurity concentration, are formed by implantation of arsenic ions, with the gate electrode 13 and the sidewall insulating films 17 and 17' serving as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a miniaturized semiconductor device.

[Summary of the invention]

In an MO3 type semiconductor device, when fabricating a so-called LDD structure in which a layer with a shallow junction and low concentration is formed for the source and drain on the side close to the channel, and a layer with a deep junction and high concentration is formed on the side far from the channel, there are many steps. A silicon oxide film (hereinafter referred to as
A commonly used method is to form a sidewall oxide film.

In the present invention, in order to obtain good device characteristics of an NMO3) transistor with an LDD structure, when forming a thinly doped source and drain on the side near the channel, phosphorus is
When ion implantation is performed at a concentration below "CIl+-" and a highly concentrated source and drain are formed on the side far from the channel by arsenic ion implantation, the length of the silicon oxide film provided on the sidewall of the gate electrode used as a mask is 0. .2 micron or more [Prior art] Fig. 2 shows a sectional view of an LDD structure. 21 is a semiconductor substrate exhibiting a certain conductivity type, 22 is a gate oxide film, 23 is polycrystalline silicon that becomes a gate electrode, 24 is a sidewall oxide film, 25 is a channel portion through which carriers flow, and 26 is a substrate on the side near the channel. 21 indicates a low concentration source/drain portion having a conductivity type opposite to that of the substrate 21, and 27 indicates a high concentration source/drain portion having a conductivity type opposite to that of the substrate 21, which is located on the side far from the channel 25.

Among the many factors that contribute to the device characteristics of an NMO3 type semiconductor transistor having an LDD structure, it has not been clear in the past which factor particularly strongly influences the device characteristics.

[Problem that the invention seeks to solve]

The drain breakdown voltage and leakage current characteristics of a MO3I-transistor are largely related to the lateral spread of the source and drain toward the channel side. If the lateral extent is large, the effective channel length will be short, the drain breakdown voltage will be low, and the leakage current will also increase.

An object of the present invention is to form an NMO3) transistor having an LDD structure so that the lateral spread of the source and drain does not become large.

[Means for solving problems]

In order to solve the above problems, this invention has a thickness of 150~
A gate insulating film of 300 angstroms is formed, a gate electrode is formed on it, and using the gate electrode as a mask, phosphorus is ion-implanted at a dose of IXIO"am-" or less, and then the gate electrode is covered. A silicon oxide film or an insulating film was deposited and etched to form a sidewall insulating film having a length of 0.2 microns or more at both lengthwise ends of the gate electrode, and then arsenic was ion-implanted at a high concentration.

[Effect]

In this way, by limiting the phosphorus dose and the length of the sidewall insulating film, it is possible to form the source and drain so that the lateral expansion does not become large, and the effective channel length of the transistor does not become short, and the drain The breakdown voltage is not low, and good NMO3I-transistor characteristics can be obtained.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(8) to 1fd) show examples of the method of manufacturing a semiconductor device of the present invention. In FIG. 1 (al), 11 is a p-type semiconductor silicon substrate, 12 is a gate oxide film made of silicon oxide with a thickness of 150 to 300 Å, 13 is a gate electrode, and 14 and 15 are lXl0, respectively.
Figure 3 shows a lightly doped source and drain formed by ion implantation of phosphorus at a dose below "cllll-".

In FIG. 1 (BL), an insulating film 16, for example, a silicon oxide film, is deposited. In FIG. Films 17 and 17' are formed.At this time, the width dimension W of the sidewall insulating film is set to be 0.2 microns or more.Next, as shown in FIG. 1(d), the gate electrode A high concentration source 18 and drain 19 are formed by arsenic ion implantation using the sidewall insulating films 17 and 17'' as masks.

In addition, a source 110 and a drain 111 having a thin concentration which have been previously implanted are formed on the channel sides of the transistors 18 and 19, respectively.

Figure 3 shows NMO3 with a gate electrode length of approximately 1.2 microns.
) Thickness t of the gate oxide film in a transistor. , I and drain breakdown voltage Bv0 are shown. The drain breakdown voltage tends to drop sharply when the gate oxide film thickness is less than about 150 angstroms. When the gate oxide film is thinner, the threshold voltage VTM of the MOS transistor when the gate electrode length is shortened tends to be lower than when the gate electrode length is long, that is, the short channel effect It is gradual. However, the electric field between the drain and the gate electrode increases as the gate oxide film becomes thinner, which lowers the drain breakdown voltage.

Drain breakdown voltage has a strong correlation with leakage current, and the lower the drain breakdown voltage, the higher the leakage current. From FIG. 3, the gate oxide film thickness is preferably 150 to 300 angstroms. When the thickness exceeds 300 angstroms, the above-mentioned short channel effect becomes noticeable and it cannot be used for fine MO3I transistors.

Figure 4 shows an NMOS with a gate electrode length of approximately 1.2 microns.
The relationship between the length W of the sidewall insulating film (FIG. 2 24) and the drain breakdown voltage of the transistor is shown. As is clear from FIG. 4, when the length W of the sidewall insulating film becomes 0.2 microns or less, the drain breakdown voltage decreases rapidly. This is due to the fact that when W becomes shorter, the concentration of the source and drain becomes lower (see Figure 2, 26).
This is because the effective length of the channel becomes shorter due to the lateral expansion of the channel. Therefore, it is desirable that the length W of this sidewall insulating film is 0.2 microns or more.

Figure 5 shows NMO3 with a gate electrode length of about 1.2 microns.
) In a transistor, the relationship between the dose of the lightly doped source and drain and the drain breakdown voltage is shown. Here, the dose species is phosphorus. As is clear from FIG. 5, when this dose exceeds 'o14 cm-', the drain breakdown voltage decreases rapidly. This is because when the dose is large, the phosphorus spreads in the lateral direction, and the channel part (Fig.
This is because the effective length of 5) becomes shorter.

When ion-implanting phosphorus to form thinly-concentrated sources and drains, the silicon oxide film of 300 angstroms or less formed on the substrate when forming the gate oxide film on the parts that will become the sources and drains is This has the effect of preventing damage to the semiconductor silicon surface. However, if the silicon oxide film is 300 angstroms thick or more, it is necessary to increase the acceleration energy during phosphorus ion implantation to about 100 KeV or more. At acceleration energies below that, l X I Q I a ,,
Even if a phosphorus dose of , -t is implanted, a phosphorus concentration of approximately IX1018 cm-3 cannot be formed near the silicon surface. If the concentration is lower than this, the resistance becomes large and the LDD function cannot be achieved.

However, when phosphorus is implanted with an acceleration energy of 100 Ke V or more, the gate electrode used as a mask has variations in grain size, especially if it is made of polycrystalline silicon.
It becomes easier for phosphorus to penetrate the gate electrode along large grains. As a result, phosphorus reaches the channel portion, lowering the Threnskjöld voltage and increasing leakage current.

Therefore, it is possible to reduce the acceleration energy of phosphorus to 100 Ke V or less, and to apply I to the lightly doped source and drain regions.
In order to obtain a surface concentration of phosphorus on the order of XIO"elm-', a silicon oxide film with a thickness of 300 angstroms or less is required on the silicon surface in regions that will become sources and drains when phosphorus is implanted.

〔Effect of the invention〕

As described above in detail, the LDD type NMO5 transistor manufactured by the manufacturing method of the present invention has excellent characteristics such as low short channel effect and low leakage current, high drain breakdown voltage, and high reliability.

[Brief explanation of the drawing]

Figure 1 +al to +dl are cross-sectional views showing the semiconductor manufacturing process of the present invention, Figure 2 is a cross-sectional view of a semiconductor device showing a conventional LDD structure, and Figure 3 is a diagram showing the relationship between gate oxide film thickness and drain breakdown voltage. , Fig. 4 is a diagram showing the relationship between the length of the sidewall insulating film and the drain breakdown voltage of the LDD structure, and Fig. 5 is a diagram showing the relationship between the length of the sidewall insulating film and the drain breakdown voltage of the LDD structure. FIG. 3 is a diagram showing the relationship between drain breakdown voltages. 11...p-type semiconductor silicon substrate or p-well 12.
...Gate oxide film 13...Gate electrodes 17, 17"...Side wall insulating film 18...High concentration source 19...High concentration drain 110...Thin Concentration source 111 ... Drain of thin concentration Applicant: Seiko Electronics Co., Ltd. (a) (b) (C) (d), Book, date of publication, publication date and time of Gyudou Ihonso J1 manufacturing odor presentation ε Figure 1 Figure 2 Dream 3

Claims (1)

[Claims] An insulating film with a thickness of 150 to 300 angstroms is formed on the main surface of the semiconductor silicon, a gate electrode is formed on it, and using the gate electrode as a mask, a 1×10^1 insulating film is passed through the insulating film into the source and drain portions. ^4cm
^-^ Phosphorus is ion-implanted at a dose of 2 or less to form an insulating film to cover the gate electrode, and sidewall insulation with a length of 0.2 micron or more is formed at both longitudinal ends of the gate electrode by etching. 1. A method of manufacturing a semiconductor device, comprising forming a film, and then ion-implanting arsenic, which is a highly concentrated N-type impurity, to form source and drain regions.