JPH01149643A - Packet buffer device - Google Patents

Abstract

PURPOSE:To make an accidentally produced error surely inspectable by comparing a zero signal outputted from a counter which counts the number of packets accumulated in a buffer memory with an address coincident signal outputted from an address comparator circuit. CONSTITUTION:When an accidental error occurs at any one of a data writing or reading-out pointer in a buffer or a counter for control and when a contradiction occurs between a buffer memory 11 and counter circuit 12, the content of the counter circuit 12 becomes zero and a zero signal is given to a coincident signal inspecting circuit 16. Then the last writing address does not coincide with the last read out address and no address coincident signal is outputted from an address comparator circuit 13. Therefore, the faulty state is detected at the coincident signal inspecting circuit 16 by inspecting the address coincident signal when the zero signal is on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet buffer device in a packet communication system.

[Conventional technology]

In packet communication systems, by sending and receiving data packets between communication devices via packet buffers, the communication devices can operate asynchronously, that is, with independent clocks, improving the reliability of the entire system against clock failures. can be done.

Many of these packet buffers have a ring configuration, and in a ring configuration buffer, a data write circuit and a data read circuit each have independent address pointers for the buffer, and write and write packets independently. The access address of a ring-configured buffer that performs a read operation has no logical end, and the physical end address is followed by the physical start address. This allows the entire buffer memory to be used effectively.

In a buffer device in which the packet write circuit and the read circuit operate independently, a communication mechanism for flow control is provided between the packet write circuit and the read circuit in order to avoid overflow and underflow of the buffer memory. It is necessary to provide Conventional buffer devices mainly employ the methods shown in i) or ii) below to realize such a flow control function. i) A method of directly comparing the write address of the packet write circuit to the buffer with the read address of the packet read circuit. However, since it is difficult to constantly compare two registers that operate asynchronously, the addresses at the time when one packet is processed in both circuits are held in separate registers and their values are compared. When there is a match, an empty signal indicating that the buffer is empty is transmitted to the packet read circuit, and when the write address is closer than a predetermined distance from the read address, a blockage signal is transmitted to the packet write circuit. method.

ii) Install a counter that indicates the number of packets in the buffer, add it when writing a packet, subtract it when reading a packet, and send a zero signal to the packet reading circuit to indicate that the number of packets in the buffer is 0. A method in which a blocking signal indicating that the number of packets exceeds a predetermined value is transmitted to the packet writing circuit.

[Problem that the invention seeks to solve]

However, in a buffer device in which the packet write circuit and read circuit operate independently, the two circuits are not directly coupled, so either one of the data in the buffer, the write or read pointer, or the control counter is When an accidental error occurs, it is difficult to detect the failure and restore the original state. Therefore, as an indirect failure detection method, there is a method of counting the length of the read packet and determining an abnormal state when the length of the read packet exceeds the maximum length of a normal packet. However, if a data error in the buffer causes two If the packets are concatenated and the total length of the concatenated packets does not exceed the maximum normal packet length, no abnormal condition is detected.

In addition, in the address comparison method described in i) above, if the address data held in the packet write address register has an error, the point of stopping the packet read circuit due to address comparison is lost, and there is a possibility of a runaway. .

Furthermore, in the method using the packet number counter mentioned above, there is a possibility that an error in the counter or an error in the data in the buffer will cause a discrepancy between the counter value and the number of packets accumulated in the buffer. There is. If the counter does not reach 0 even though the packet reading circuit has read all the packets in the buffer, the reading circuit does not stop reading packets and sometimes reads old data written in the buffer. Sometimes,
The above-mentioned indirect fault detection means cannot reliably detect faults. Also, if the counter reaches O before the read circuit has read all the packets in the buffer, the read circuit will stop reading packets, but no fault condition will be detected.

As described above, a buffer management means that cannot reliably detect an abnormal state has a problem in that a highly reliable buffer device cannot be realized.

An object of the present invention is to provide a highly reliable packet buffer device that can reliably detect accidental errors and restore the normal state.

[Means for solving problems]

The packet buffer device of the present invention includes a ring-configured buffer memory that temporarily stores packets, writes packets arriving from the outside into the buffer memory, and outputs a write end pulse when writing of one packet is completed. , a packet write circuit that holds and outputs the final address when writing of the packet was completed last; and a packet write circuit that reads the packet from the buffer memory and sends it to the outside.
A packet readout circuit outputs a readout end pulse when the reading of one packet is completed, and holds and outputs the final address when the readout of the packet is finally completed; a counter circuit having an up/down counter that is subtracted by the end pulse and outputting a zero signal indicating that the content of the counter is 0 to the packet readout circuit;
modulo subtracting the final address when the last packet reading was completed from the final address when the last packet writing was completed, and outputting an address match signal indicating that the result of the calculation is 0; an address comparison circuit that outputs a blockage signal to the packet writing circuit when the calculation result is less than a preset threshold; and an address comparison circuit that inspects the address match signal when the zero signal is output, and detects a discrepancy in the inspection result. The device includes a coincidence signal check circuit that sends a reset signal to the packet write circuit, the packet read circuit, and the counter circuit.

[Effect]

FIG. 1 is a block diagram showing the configuration of a packet buffer device according to the present invention. In FIG. 1, 11 is a ring-configured buffer memory, 12 is a counter circuit, 13 is an address comparison circuit, 14 is a packet write circuit, 15 is a packet read circuit, 16 is a coincidence signal check circuit, and 17 is a packet input from outside. Reference numeral 18 indicates a terminal for sending packets to the outside.

When one packet enters from the terminal 17, the packet write circuit 14 writes to the buffer memory 11, and when the writing is completed, the write address is latched and transmitted to the address comparison circuit 13, and the counter circuit 12
Give a write end pulse to. Packet reading circuit 15
monitors the signal input from the counter circuit 12 when the counter value is 0, starts reading packets from the buffer memory 11 when this signal is off, and sends the read data to the terminal 18. Furthermore, when the packet readout circuit 15 completes the readout of one packet, it latches the readout address and transmits it to the address comparison circuit 13, and also provides a readout end pulse to the counter circuit 128.

In this configuration, the counter circuit 12 is incremented (+1) at the end of packet writing and subtracted (-1) at the end of packet reading, so that it always indicates the number of packets in the buffer memory 11 during normal operation. When the content of the counter is 0, the counter circuit 12 outputs a zero signal to the packet reading device 15 to stop the packet reading operation.

On the other hand, the address comparison circuit 13 always measures the distance between the final write address input from the packet write circuit 14 and the final read address input from the packet read circuit 15, and measures the distance from the write address to the read address. If the distance is closer than a preset value stored inside the address comparison circuit, a blockage signal is output to the packet write circuit 14 to stop the packet write operation.

As described above, by applying a zero signal to the packet write circuit and a blockage signal to the packet read circuit 15 during normal operation, it is possible to realize write/read flow control for the buffer memories 7 and 11. By the way, during normal operation, the number of packets stored in the buffer memory 11 and the contents of the counter circuit 12 match, so that the contents of the counter circuit 12 are 0, that is, a zero signal is given to the coincidence signal checking circuit 16. When there is no packet in the buffer memory 11, the final write address and the final read address match,
The address comparison circuit 13 should have given the address match signal to the match signal check circuit 16. Conversely, if an accidental error occurs in the data in the buffer, the write or read pointer, or the control counter,
If a contradiction occurs between the buffer memory 11 and the counter circuit 12, when the contents of the counter circuit 12 become 0 and a zero signal is given to the coincidence signal check circuit 16, the final write address and the final read address are The address does not match, and the address match signal is not detected. Therefore, the coincidence signal inspection circuit 16 detects a failure state by inspecting the address coincidence signal when the zero signal is on, and sends a reset signal to the packet write circuit 14 and the packet read circuit 15.
, and can be fed back to the counter circuit 12. By resetting the counter circuit 12 with a reset signal and initializing the write address pointer of the packet write circuit 14 and the read address pointer of the packet read circuit 15, the normal state can be restored.

〔Example〕

Hereinafter, an embodiment of the main circuit of the packet buffer device of the present invention shown in FIG. 1 will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the address comparison circuit 13. In FIG. 2, 21 is a modulo subtraction circuit;
2 is a subtraction circuit, 23 is a zero judgment circuit, 24 is a fixed register, 25 is a terminal for inputting write address data from the packet write circuit 14, and 26 is a packet read circuit 15.
27 is a terminal for transmitting the output of the zero judgment circuit to the coincidence signal checking circuit 16 as an address match signal. 28 is a terminal for transmitting the output of the sign bit of the operation result of the subtraction circuit 22 to the packet as a blocking signal. A terminal for transmitting data to the write circuit 14 is shown.

The modulo subtraction circuit 21 is a subtraction circuit that subtracts the write address data given from the packet write circuit 15 via the terminal 25 from the read address data given from the packet read circuit 14 via the terminal 26, and the operation result is negative. In this case, the physical address space length of the buffer memory 11 is added, the logical distance between the two addresses on the buffer memory 11 is calculated, and the result is output to the subtraction circuit 22 and the zero determination circuit 23. . The subtraction circuit 22 outputs the fixed register 2 from the modulo subtraction circuit 21 output.
Signed subtraction is performed to subtract the value stored in 4, and the sign bit is output to terminal 28. The zero judgment circuit 23 turns on when the output of the modulo subtraction circuit 21 is 0.
When the value is not 0, an off signal is output to the terminal 27.

FIG. 3 is a block diagram of one embodiment of the counter circuit 12. In FIG. 3, 31 is a counter, 32 is a zero judgment circuit, 33 is a terminal for inputting the write end pulse from the packet write circuit 14, 34 is a terminal for inputting the read end pulse from the packet read circuit 15, and 35 is a zero judgment circuit. A terminal for outputting the output of 32 to the packet readout circuit and the coincidence signal inspection circuit 16; 36 is the coincidence signal inspection circuit 16;
This shows the terminal that inputs the reset signal coming from.

The counter 31 is an up/down counter that adds up with pulses input from a terminal 33 and subtracts with pulses input from a terminal 34, and outputs its contents to the zero determination circuit 32. Further, the counter 31 is reset by a reset signal received from the coincidence signal checking circuit 16 via the terminal 36. The zero determination circuit 32 outputs ON to the terminal 35 when the output of the counter 31 is O, and outputs OFF when the output is not O.

FIG. 4 is a block diagram showing one embodiment of the coincidence signal checking circuit 16. In FIG. 4, 41 is an AND circuit, 42
is a NOT circuit, 43 is a single terminal that inputs the signal coming from the address comparison circuit 13, 44 is a terminal that inputs the address match signal coming from the counter circuit 12, and 45 is an AN
A terminal is shown in which the output of the D circuit 41 is fed back to the address comparison circuit 13, packet writing device 14, and packet reading device 15 as a reset signal.

〔Effect of the invention〕

According to the present invention, the present invention includes a counter that counts the number of packets accumulated in a buffer memory, and a circuit that compares a write address pointer and a read address pointer for the buffer, and a zero signal outputted from the counter and a circuit that compares a write address pointer and a read address pointer for the buffer. By comparing the address match signal output from the address comparison circuit, it is possible to reliably check for errors that occur by chance, and it is possible to provide a highly reliable buffer device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a packet buffer device according to the present invention, FIG. 2 is a block diagram of an embodiment of the address comparison circuit of FIG. 1, and FIG. 3 is an implementation of the counter circuit of FIG. 1. Example Block Diagram FIG. 4 is a block diagram of one embodiment of the coincidence signal checking circuit of FIG. 11... Buffer memory, 12... Counter circuit,
13...Address comparison circuit, 14...Packet write circuit, 15...Packet read circuit, 16...Coincidence signal inspection circuit, 21...Modulo subtraction circuit, 22...
...Subtraction circuit, 23.23...Zero judgment circuit, 24.
...Fixed register, 31...Counter.

Claims (1)

[Claims] A buffer memory with a ring configuration that temporarily stores packets, and packets arriving from the outside are written to the buffer memory, and a write end pulse is output when writing of one packet is completed, and finally writing of the packet is completed. A packet write circuit holds and outputs the final address when the packet is read, reads the packet from the buffer memory and sends it to the outside, outputs a read end pulse when reading of one packet is completed, and finally writes the final address of the packet. It has a packet readout circuit that holds and outputs the final address when reading is completed, and an up/down counter that is added by the write end pulse and subtracted by the read end pulse, and the content of this counter is 0. a counter circuit that outputs a zero signal to the packet readout circuit to indicate that the packet has read out; an address comparison circuit that outputs an address match signal indicating that the result is 0, and outputs a blockage signal to the packet writing circuit when the operation result is less than a preset threshold; The device is characterized by comprising a coincidence signal inspection circuit that sometimes inspects the address coincidence signal and sends a reset signal to the packet write circuit, the packet read circuit, and the counter circuit when a mismatch is found in the inspection result. Packet buffer device.